DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-16 in the reply filed on 05/18/26 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Radic(USPATENT: 11018247, hereinafter Radic) in view of Adkisson (USPGPUB DOCUMENT: 2015/0311283, hereinafter Adkisson).
Re claim 1 Radic discloses in Fig 2 a method comprising: providing a substrate(210) that includes a dielectric isolation region(269) and a collector region(220) that includes semiconductor material[col6, lines 25-40]; forming a polycrystalline semiconductor layer(240)[col5,lines 35-65] over the substrate(210); forming a intrinsic base layer, wherein the intrinsic base layer(230) is in direct contact with the polycrystalline semiconductor layer(240)[col5,lines 35-65]; and forming a monocrystalline extrinsic base layer(282)[col10,lines 5-25], wherein the monocrystalline extrinsic base layer(282)[col10,lines 5-25] .
Radic does not disclose forming a monocrystalline intrinsic base layer via epitaxial growth, removing the polycrystalline semiconductor layer(240)[col5,lines 35-65] after forming the monocrystalline intrinsic base layer; and forming a monocrystalline extrinsic base layer(282)[col10,lines 5-25] via epitaxial growth, wherein the monocrystalline extrinsic base layer(282)[col10,lines 5-25] is in direct contact with the monocrystalline intrinsic base layer.
Adkisson disclose forming a monocrystalline intrinsic base layer(10)[0011 of Adkisson] via epitaxial growth, removing (see Fig 3-4 of Adkisson) the polycrystalline semiconductor layer(22 of Adkisson) after forming the monocrystalline intrinsic base layer;
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Adkisson to the teachings of Radic in order to enhance device performance [0004, Adkisson]. In doing so, forming a monocrystalline extrinsic base layer(282)[col10,lines 5-25] via epitaxial growth[0011 of Adkisson], wherein the monocrystalline extrinsic base layer(282)[col10,lines 5-25] is in direct contact with the monocrystalline intrinsic base layer(10)[0011of Adkisson].
Re claim 2 Radic and Adkisson disclose the method of claim 1, further comprising: forming a dielectric spacer structure by: forming a first spacer layer over the substrate(210); forming a second spacer layer over the substrate(210); etching portions of the second spacer layer; and etching portions of the first spacer layer, wherein the dielectric spacer structure is disposed over the monocrystalline intrinsic base layer.
Re claim 3 Radic and Adkisson disclose the method of claim 2, further comprising: forming a polycrystalline emitter layer and a monocrystalline emitter layer over the substrate(210) via epitaxial growth, wherein the polycrystalline emitter layer at least partially overlaps the monocrystalline extrinsic base layer(282)[col10,lines 5-25], the monocrystalline emitter layer overlaps the monocrystalline intrinsic base layer, and the dielectric spacer structure is interposed between the monocrystalline extrinsic base layer(282)[col10,lines 5-25] and the monocrystalline emitter layer and is interposed between the polycrystalline emitter layer and the monocrystalline intrinsic base layer.
Re claim 4 Radic and Adkisson disclose the method of claim 2, wherein removing the polycrystalline semiconductor layer(240)[col5,lines 35-65] and forming the monocrystalline extrinsic base layer(282)[col10,lines 5-25] are performed after etching the portions of the second spacer layer.
Re claim 5 Radic and Adkisson disclose the method of claim 2, wherein removing the polycrystalline semiconductor layer(240)[col5,lines 35-65] and forming the monocrystalline extrinsic base layer(282)[col10,lines 5-25] are performed before forming the dielectric spacer structure.
Re claim 6 Radic and Adkisson disclose the method of claim 2, wherein removing the polycrystalline semiconductor layer(240)[col5,lines 35-65] and forming the monocrystalline extrinsic base layer(282)[col10,lines 5-25] are performed after forming the first spacer layer and forming the second spacer layer and before etching the portions of the second spacer layer and etching the portions of the first spacer layer.
Re claim 7 Radic and Adkisson disclose the method of claim 2, further comprising: forming a first dielectric stack on the polycrystalline semiconductor layer(240)[col5,lines 35-65]; and forming an emitter window by etching a first opening in the first dielectric stack and the polycrystalline semiconductor layer(240)[col5,lines 35-65], wherein the first opening exposes an upper surface of the collector region(220), wherein the dielectric spacer structure is formed in the emitter window.
Re claim 8 Radic and Adkisson disclose the method of claim 7, further comprising: forming a launcher layer on the exposed surface of the collector region(220) via selective epitaxial growth, wherein forming the monocrystalline intrinsic base layer further includes forming the monocrystalline intrinsic base layer on the launcher layer via selective epitaxial growth; and forming an emitter cap layer on the intrinsic base layer(230), wherein the emitter cap layer and the launcher layer each comprise silicon.
Re claim 9 Radic discloses in Fig 2 a method of fabricating a transistor device, the method comprising: forming, a polycrystalline semiconductor layer(240)[col5,lines 35-65] over an isolation region(269) and a collector region(220) of substrate(210); forming, a monocrystalline extrinsic base layer(282)[col10,lines 5-25].
Radic does not disclose forming, via selective epitaxial growth, a monocrystalline intrinsic base layer over the collector region(220); removing the polycrystalline semiconductor layer(240)[col5,lines 35-65] via one or more etch processes; and forming, via selective epitaxial growth, a monocrystalline extrinsic base layer(282)[col10,lines 5-25] that directly contacts the monocrystalline intrinsic base layer.
Adkisson disclose forming, via selective epitaxial growth, a monocrystalline intrinsic base layer(10)[0011 of Adkisson]; removing(see Fig 3-4 of Adkisson) the polycrystalline semiconductor layer(22 of Adkisson) via one or more etch processes;
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Adkisson to the teachings of Radic in order to enhance device performance [0004, Adkisson]. In doing so, a monocrystalline intrinsic base layer(10)[0011 of Adkisson] over the collector region(220); and forming, via selective epitaxial growth[0011 of Adkisson], a monocrystalline extrinsic base layer(282)[col10,lines 5-25] that directly contacts the monocrystalline intrinsic base layer(10)[0011of Adkisson].
One or more etch processes for a removal process would have been obvious because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. KSR, see MPEP 2143.
Re claim 10 Radic and Adkisson disclose the method of claim 9, further comprising: forming a dielectric spacer structure by: forming a first spacer layer over the substrate(210); forming a second spacer layer over the substrate(210); etching portions of the second spacer layer; and etching portions of the first spacer layer, wherein the dielectric spacer structure is disposed over the monocrystalline intrinsic base layer.
Re claim 11 Radic and Adkisson disclose the method of claim 10, further comprising: forming a polycrystalline emitter layer and a monocrystalline emitter layer over the substrate(210) via epitaxial growth, wherein the polycrystalline emitter layer at least partially overlaps the monocrystalline extrinsic base layer(282)[col10,lines 5-25], the monocrystalline emitter layer overlaps the monocrystalline intrinsic base layer, and the dielectric spacer structure is interposed between the monocrystalline extrinsic base layer(282)[col10,lines 5-25] and the monocrystalline emitter layer and is interposed between the polycrystalline emitter layer and the monocrystalline intrinsic base layer.
Re claim 12 Radic and Adkisson disclose the method of claim 10, wherein removing the polycrystalline semiconductor layer(240)[col5,lines 35-65] and forming the monocrystalline extrinsic base layer(282)[col10,lines 5-25] are performed after etching the portions of the second spacer layer.
Re claim 13 Radic and Adkisson disclose the method of claim 10, wherein removing the polycrystalline semiconductor layer(240)[col5,lines 35-65] and forming the monocrystalline extrinsic base layer(282)[col10,lines 5-25] are performed before forming the dielectric spacer structure.
Re claim 14 Radic and Adkisson disclose the method of claim 10, wherein removing the polycrystalline semiconductor layer(240)[col5,lines 35-65] and forming the monocrystalline extrinsic base layer(282)[col10,lines 5-25] are performed after forming the first spacer layer and forming the second spacer layer and before etching the portions of the second spacer layer and etching the portions of the first spacer layer.
Re claim 15 Radic and Adkisson disclose the method of claim 10, further comprising: forming a first dielectric stack on the polycrystalline semiconductor layer(240)[col5,lines 35-65]; and forming an emitter window by etching a first opening in the first dielectric stack and the polycrystalline semiconductor layer(240)[col5,lines 35-65], wherein the first opening exposes an upper surface of the collector region(220), wherein the dielectric spacer structure is formed in the emitter window.
Re claim 16 Radic and Adkisson disclose the method of claim 15, further comprising: forming a launcher layer on the exposed surface of the collector region(220) via selective epitaxial growth, wherein forming the monocrystalline intrinsic base layer further includes forming the monocrystalline intrinsic base layer on the launcher layer via selective epitaxial growth; and forming an emitter cap layer on the intrinsic base layer(230), wherein the emitter cap layer and the launcher layer each comprise silicon.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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