DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species A, represented by figures 1A-1C and 4-25, and claims 1-11, 14-17, and 19-20 in the reply filed on July 15, 2026 is acknowledged. The traversal is on the ground(s) that Species A and Species B are not distinct from each as they are both directed to a channel material layer. This is not found persuasive because the Species stated by Examiner are directed to different methods of forming different final products. One of the final products has 44’ partially surrounded by 44, and the other final product has no 44’. These two final products require different methods to form them. Further, Applicant has not stated they are obvious variants of each other.
Therefore, the requirement is still deemed proper and is therefore made FINAL.
Accordingly, claim 12-13, 18-25 are hereby withdrawn.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 2, 2024 was considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, and 11 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hwang (US 2025/0089238 A1) (“Hwang”).
Regarding claim 1, Hwang teaches:
forming a cell mold including (detailed below)
a dummy channel pattern (DM1) and a plurality of mold layers (GN1) over a lower structure (¶ 0064 substrate not shown);
forming a horizontal conductive line (WM1) that intersects with the dummy channel pattern (DM1);
forming a dummy channel layer by trimming the dummy channel pattern (figure 38B-39B);
forming a data storage element (EL1/DL1/PL1) that is coupled to a first side of the dummy channel layer (figure 50A);
replacing the dummy channel layer (DM1) with a channel layer (CM1) (Figure 53A); and
forming a vertical conductive line (BL1) that is coupled to a second side of the channel layer (CM1) (figure 55A).
Regarding claim 2, Hwang teaches:
wherein the replacing the dummy channel layer with the channel layer includes (detailed below):
forming a channel level gap by removing the dummy channel layer (this is shown in figure 52A);
forming a channel material layer over the channel level gap (this is shown in figure 53A); and
forming the channel layer by selectively removing the channel material layer (this is shown in figure 54A).
Regarding claims 3, and 11, Hwang teaches:
wherein the dummy channel pattern (DM1) and the dummy channel layer (DM1) include a silicon material (¶ 0143), and
the channel layer (CM1) includes an oxide semiconductor material (¶ 0078).
Regarding claim 4, Hwang teaches:
before the forming of the horizontal conductive line that intersects with the dummy channel pattern, forming a gate dielectric layer (GN1) on top and bottom surfaces of the dummy channel pattern (DM1), individually (this is shown in figure 33B).
Regarding claim 6, Hwang teaches:
wherein the forming the horizontal conductive line that intersects with the dummy channel pattern includes (detailed below):
forming horizontal level recesses that intersect with the dummy channel pattern by removing the mold layers of the cell mold; (this is shown in figure 35B with element H20)
forming a conductive material (WM1) over the horizontal level recesses (this is shown in figure 36A); and
forming the horizontal conductive line by selectively etching the conductive material (this is shown in figure 37A).
Claim Rejections - 35 USC § 102
and/or
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 102(a)(2)) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Hwang.
Regarding claim 7, Hwang teaches:
wherein the forming the cell mold including the dummy channel pattern includes (detailed below):
forming the dummy channel pattern (DM1) over the lower structure (¶ 0064 substrate not shown);
forming a first cell dielectric layer (GN1) that surrounds the dummy channel pattern (DM1); and
forming a second cell dielectric layer that surrounds the first cell dielectric layer (¶ 0077, where GN1 can include at least one of the listed materials. The term “at least one” means that one may use more than one of the listed materials, but at least one of the listed materials must be used. Therefore, this term allows for more than one dielectric material to be used at the same time. This means one can form a first dielectric layer formed of at least one of the materials, and a second dielectric layer on the first dielectric layer formed of another of the at least one of listed materials. Alternatively, it would have been obvious that based upon the broad language of the disclosure that one of ordinary skill in the art would have known that they could use a plurality of gate dielectric layers (first cell dielectric layer and second cell dielectric layer) surrounding the dummy channel layer.).
Regarding claim 8, Hwang teaches:
wherein the first cell dielectric layer includes silicon nitride, and the second cell dielectric layer includes silicon oxide (¶ 0077, where silicon nitride and silicon oxide are in the taught material list).
Allowable Subject Matter
Claim 5, 9-10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, Hwang does not teach:
wherein the forming the gate dielectric layer includes exposing the top and bottom surfaces of the dummy channel pattern to a thermal oxidation process.
As shown in figures 5A-6B, the gate dielectric (GN1) is formed before forming the dummy channel pattern (DM1).
Regarding claim 9, Hwang does not teach:
wherein the forming the cell mold including the dummy channel pattern includes:
forming a stacked structure that includes a dummy channel material layer over the lower structure and sacrificial layers respectively disposed on the top and bottom surfaces of the dummy channel material layer;
forming openings by etching portions of the stacked structure;
removing the sacrificial layers through the openings; and forming the dummy channel pattern by thinning the dummy channel material layer through the openings.
This is because Hwang does not teach forming the sacrificial layers, and the subsequent processing of said sacrificial layers.
Claims 14-17 are allowed.
The following is an examiner’s statement of reasons for allowance: see below.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Regarding claim 14,
Claim 14 contains similar, or substantially the same, limitation as claim 5 above, and is allowable for the same reasons as given in claim 5 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST.
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/VINCENT WALL/ Primary Examiner, Art Unit 2898
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