DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on February 8, 2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 2, 2024, April 22, 2024 is being considered by the examiner.
Election/Restrictions
Claims 8 and 10-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected device embodiment, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on August 17, 2026.
Applicant's election with traverse of Species I (claims 1-7 and 9) in the reply filed on August 17, 2026 is acknowledged. The traversal is on the ground(s) that the species have significant overlap in subject matter as the gate connection structure is included in both claims 1 and 10. This is not found persuasive because as stated in the restriction requirement of June 18, 2026, embodiment 1 (Figs. 1 and 7) do not have a side dielectric layer like 170 of Fig. 4A and would result in a divergent search.
The requirement is still deemed proper and is therefore made FINAL.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Device With Gate Connection Structure
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines: 7-8 recite the limitation “a gate connection structure located between the first gate electrode and the second gate electrode and respectively connecting the first gate electrode and the second gate electrode…” it is unclear if respectively connecting the first gate electrode and the second gate electrode means that the gate connection structure is connected to respectively to each of the first and second gate electrode or if the gate connection structure respectively connects the first and second gate electrode to one another. For purposes of examination this will be interpreted as “a gate connection structure located between the first gate electrode and the second gate electrode and respectively connecting the first gate electrode and the second gate electrode to one another…”
Claim 5, line 3 recites the limitation “the gate connection structure connects the third gate electrode…” it is unclear if the gate connection structure connects to the third gate electrode or if the gate connection structure connects the third gate electrode to the other two gate electrodes. For purpose of examination this will be interpreted as “the gate connection structure connects to the third gate electrode…”
Claim 6 recites the limitation "the polygon " in line 3. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the polygon shape”
Allowable Subject Matter
Claims 1-7 and 9 would be allowed if rewritten to overcome the 112 rejection above.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Yamagiwa (US 2024/0304630), Hadizad (US 2005/0056893), Kumar (US 2005/0145852), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 1 (from which claims 2-7 and 9 depend), an area of a vertical projection of the gate connection structure on the substrate is smaller than an area of a vertical projection of the extension portion of the gate insulation layer on the substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yamagiwa (US 2024/0304630) discloses (Fig. 12) gate electrodes 914 connected to gate collecting line 974 between source lines 915. Yamagiwa does not disclose the gate insulation layer comprises an extension portion located between the first gate electrode and the second gate electrode, and an area of a vertical projection of the gate connection structure on the substrate is smaller than an area of a vertical projection of the extension portion of the gate insulation layer on the substrate.
Hadizad (US 2005/0056893) discloses (Fig. 1) drain 88 on bottom substrate 14 and plurality of gates 66 connected by metal layer 87. Hadizad does not disclose the gate insulation layer comprises an extension portion located between the first gate electrode and the second gate electrode, and an area of a vertical projection of the gate connection structure on the substrate is smaller than an area of a vertical projection of the extension portion of the gate insulation layer on the substrate.
Kumar (US 2005/0145852) discloses (Fig. 2) a semiconductor device, comprising: a drain electrode (12); a substrate (1) located on the drain electrode (12); a first source contact (left 20) and a second source contact (right 20) located on the substrate; a first gate electrode (frontmost GATE) and a second gate electrode (middle GATE) located on the substrate and are located between the first source contact and the second source contact (GATEs between 20s); a gate connection structure (10) located between the first gate electrode and the second gate electrode and respectively connecting the first gate electrode and the second gate electrode to one another (10 is between GATEs and connects them together); and a gate insulation layer (9) surrounding the first gate electrode, the second gate electrode, and the gate connection structure (9 surrounds GATEs and 10). Kumar does not disclose wherein the gate insulation layer comprises an extension portion located between the first gate electrode and the second gate electrode, and an area of a vertical projection of the gate connection structure on the substrate is smaller than an area of a vertical projection of the extension portion of the gate insulation layer on the substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
Prosecution Insights