Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 02/17/2026 have been fully considered but they are not persuasive.
Applicant submits that Mattos and Ostrovsky, taken alone or in combination, do not teach, suggest, or contemplate outputting a reference signal, let alone "a combined connection at which a combined signal is provided, wherein the combined signal is indicative of the fault signal during times when the fault is detected and the reference voltage during times when the fault is not detected," as claimed. The examiner respectfully disagrees. Claims 1 and 14 as currently presented does not recite “outputting a reference signal”. Hence, this statement is moot. Regarding the newly presented limitations “a combined connection at which a combined signal is provided, wherein the combined signal is indicative of the fault signal during times when the fault is detected and the reference voltage during times when the fault is not detected” in claims 1 and 14, Mattos teaches wherein the output signal Out_d is a digital logic gate output of ONE or ZERO from an AND gate based on the output of comparator 150, which compares a sensed voltage to the selected reference voltage. The output signal Out_d in Mattos is the equivalent to the claimed combined signal, because the digital logic gate output of one or zero will indicate whether a fault is detected or not. In the case a fault exists, the output signal OUT_d will indicate a one, which is the representation of a fault signal; and when a fault doesn’t exist, the output signal OUT_d will indicate a zero, which is the representation of a reference signal. Therefore, Mattos can be reasonably construed as teaching “a combined connection at which a combined signal is provided, wherein the combined signal is indicative of the fault signal during times when the fault is detected and the reference voltage during times when the fault is not detected”, as claimed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 7-9, 11-12, 14-15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mattos et al. (US PGPUB 2017/0331270) in view of Ostrovsky (US PGPUB 2022/0294204).
Regarding claims 1 and 14, Mattos et al. teaches a method and sensor integrated circuit configured to generate a sensor output signal indicative of a sensed parameter, comprising: a power connection (vddd connected to 160, as shown in fig. 1) configured to receive a supply voltage; a ground connection (pad_vgnd connected to 160, as shown in fig. 1); a sensing circuit (110) configured to generate the sensor output signal (Out1) at a sensor output signal connection; a fault circuit (140) comprising a fault detector (150) configured to detect a fault and generate a fault signal (Out2, as shown in fig. 3) indicative of the fault; and a combined connection (Out_d, as shown in fig. 3) at which a combined signal is provided, wherein the combined signal is indicative of the fault signal during times when the fault is detected and the reference voltage (Vref) during times when the fault is not detected (see response to arguments section above).
Mattos et al. fails to specifically teach wherein the sensing circuit has a reference voltage. However, Ostrovsky teaches wherein the sensing circuit (110) has a reference voltage (Vref) (as shown in fig. 2).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the sensing circuit have a reference voltage
as taught by Ostrovsky with the invention of Mattos et al. in order to recognize an acceptable range for Vref and extrapolate information about the power supplied to the sensor integrated circuit based on Vref.
Regarding claims 2 and 15, the combination of Mattos et al. and Ostrovsky teaches the limitations of claims 1 and 14, in addition, Mattos et al. teaches a reference buffer (456) coupled to receive the reference voltage (as disclosed in para. 0046).
Regarding claims 7 and 20, the combination of Mattos et al. and Ostrovsky teaches the limitations of claims 1 and 14, in addition, Mattos et al. teaches wherein the fault is an overcurrent condition.
Regarding claim 9, the combination of Mattos et al. and Ostrovsky teaches the limitations of claims 1, in addition, Mattos et al. teaches wherein the sensing circuit comprises a sensing element (sense resistor) configured to generate a sensing element output signal and a processing path responsive to the sensing element output signal and configured to generate the sensor output signal (as shown in fig. 1 and disclosed in para. 0025).
Regarding claim 11, the combination of Mattos et al. and Ostrovsky teaches the limitations of claims 9, in addition, Mattos et al. teaches wherein the processing path comprises a front-end amplifier (114) coupled to receive the sensing element output signal and configured to generate an amplifier output signal (as shown in fig. 1 and disclosed in para. 0025).
Regarding claim 12, the combination of Mattos et al. and Ostrovsky teaches the limitations of claims 1.
Mattos et al. fails to specifically teach wherein the reference voltage is at a voltage level of approximately one-half the supply voltage. However, Ostrovsky teaches wherein the reference voltage is at a voltage level of approximately one-half the supply voltage (as disclosed in para. 0053).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the reference voltage at a voltage level of approximately one-half the supply voltage as taught by Ostrovsky with the invention of Mattos et al. in order to use a value that it is easier to compare to the original voltage supplied.
Claims 3 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Mattos et al. (US PGPUB 2017/0331270) and Ostrovsky (US PGPUB 2022/0294204) as applied to claims 2 and 15 above, and further in view of Le Goff et al. (US PGPUB 2022/0034684).
Regarding claims 3 and 16, the combination of Mattos et al. and Ostrovsky teaches the limitations of claims 2 and 15.
The combination of Mattos et al. and Ostrovsky fails to specifically teach wherein the fault detector is further configured to generate a disable signal coupled to the reference buffer and configured to disable the reference buffer when a fault is detected. However, Le Goff et al. teaches wherein the fault detector (200) is further configured to generate a disable signal coupled to the reference buffer and configured to disable the reference buffer (285) when a fault is detected (as disclosed in para. 0046).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the fault detector configured to generate a disable signal coupled to the reference buffer and configured to disable the reference buffer when a fault is detected as taught by Le Goff et al. with the invention of the combination of Mattos et al. and Ostrovsky in order to set the output of the sensor integrated circuit to a high impedance state.
Claims 4-6, 8, 10, 13, 17-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Mattos et al. (US PGPUB 2017/0331270) and Ostrovsky (US PGPUB 2022/0294204) as applied to claims 1, 7, 9 and 14 above, and further in view of Fernandez (US PGPUB 2018/0136999).
Regarding claims 4 and 17, the combination of Mattos et al. and Ostrovsky teaches the limitations of claims 1 and 14.
The combination of Mattos et al. and Ostrovsky fails to specifically teach wherein the fault signal is a digital signal having a low level when a fault is detected. However, Fernandez teaches wherein the fault signal is a digital signal having a low level when a fault is detected (as disclosed in para. 0045-0048).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the fault signal as a digital signal having a low level when a fault is detected as taught by Fernandez with the invention of the combination of Mattos et al. and Ostrovsky in order to turn on/off other devices on the sensor integrated circuit.
Regarding claims 5 and 18, the combination of Mattos et al., Ostrovsky and Fernandez teaches the limitations of claims 4 and 17, in addition, Fernandez teaches wherein the fault circuit further comprises a pull-down transistor (216’) controlled by the fault signal and configured to pull the combined signal to the low level when the fault is detected (as disclosed in para. 0045-0048).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the fault circuit comprise a pull-down transistor controlled by the fault signal and configured to pull the combined signal to the low level when the fault is detected as taught by Fernandez with the invention of the combination of Mattos et al. and Ostrovsky in order to avoid damage to components in the sensor integrated circuit.
Regarding claims 6 and 19, the combination of Mattos et al., Ostrovsky and Fernandez teaches the limitations of claims 4 and 17, in addition, Fernandez teaches wherein the fault is a first fault and the fault detector is further configured to detect a second fault (as disclosed in para. 0045-0048), and wherein the fault circuit further comprises a push-pull circuit (216’) controlled by the fault signal and configured to pull the combined signal to the low level when the first fault is detected and pull the combined signal to a high level when the second fault is detected (as disclosed in para. 0045-0048).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the fault as a first fault and the fault detector is further configured to detect a second fault, and wherein the fault circuit further comprises a push-pull circuit controlled by the fault signal and configured to pull the combined signal to the low level when the first fault is detected and pull the combined signal to a high level when the second fault is detected as taught by Fernandez with the invention of the combination of Mattos et al. and Ostrovsky in order to avoid damage to components in the sensor integrated circuit.
Regarding claims 8 and 21, the combination of Mattos et al. and Ostrovsky teaches the limitations of claims 7 and 14.
The combination of Mattos et al. and Ostrovsky fails to specifically teach wherein the sensed parameter is a current flow through a conductor and the overcurrent condition is an overcurrent condition of the current flow through the conductor. However, Fernandez teaches wherein the sensed parameter is a current flow through a conductor and the overcurrent condition is an overcurrent condition of the current flow through the conductor (as disclosed in para. 0027).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the sensed parameter as a current flow through a conductor and the overcurrent condition as an overcurrent condition of the current flow through the conductor as taught by Fernandez with the invention of the combination of Mattos et al. and Ostrovsky in order to have the ability to detect variations in a magnetic field.
Regarding claim 10, the combination of Mattos et al. and Ostrovsky teaches the limitations of claim 9.
The combination of Mattos et al. and Ostrovsky fails to specifically teach wherein the sensing element comprises a magnetic field sensing element and the sensed parameter is a magnetic field. However, Fernandez teaches wherein the sensing element comprises a magnetic field sensing element and the sensed parameter is a magnetic field (as disclosed in para. 0027).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the sensing element comprise a magnetic field sensing element and the sensed parameter is a magnetic field as taught by Fernandez with the invention of the combination of Mattos et al. and Ostrovsky in order to have the ability to detect variations in a magnetic field.
Regarding claim 13, the combination of Mattos et al. and Ostrovsky teaches the limitations of claim 1.
The combination of Mattos et al. and Ostrovsky fails to specifically teach wherein the combined connection is configured for coupling to an external buffer or an external inverter to generate a level-shifted combined signal. However, Fernandez teaches wherein the combined connection is configured for coupling to an external buffer or an external inverter (304) to generate a level-shifted combined signal (high or low signal) (as disclosed in para. 0040-0041).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the combined connection configured for coupling to an external buffer or an external inverter to generate a level-shifted combined signal as taught by Fernandez with the invention of the combination of Mattos et al. and Ostrovsky in order to pivot between different actions based on different outcomes.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fernandez (US PGPUB 2018/0136999) teaches a diagnostic fault communication.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERTO VELEZ whose telephone number is (571)272-8597. The examiner can normally be reached Mon-Fri 5:30am-3:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERTO VELEZ/Primary Examiner, Art Unit 2858