DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election, with traverse, Invention I directed to a chip packaging structure and its Species shown in Fig. 6A in the Response to the Restriction Requirements filed on 05/26/26 is acknowledged.
Together with the Response, Applicant cancelled Claim 7 and amended independent Claims 1, 12, and 17 with a limitation claiming a ring.
Traversal of the Restriction Requirements was based on an argument that
US 20210098421 (Wu et al.), referred to by the Restriction Requirements as a proof of absence a special technical feature uniting three inventions, would not be applicable for the set of amended claims claiming a ring, which, per Applicant, allows linking all inventions together.
Agreeing with Applicant that a ring, as it is claimed by Claim 1, is not taught by Wu, Examiner disagrees that this feature is patentable, since the current Office Action shows that using a ring in a manner claimed by Claim 1 is known in the art. Note that Wu also teaches a ring (Figs. 1F and 2), but its disposition is different from what Claim 1 claims. Accordingly, the set of amended claims still has no special technical feature, which still allows to restrict different inventions, as well as to restrict a single invention based on different species.
Applicant stated that Claims 1-6 and 8-11 are read on the chosen Species (of Fig. 6A). However,
Claim 8, reciting a heat dissipating lid (e.g., element 19 in some figures of the application) is not read on Fig. 6A, but is read on Fig. 6C;
Claim 9, reciting a third packaging layer (e.g., element 19’ in some figures of the application) is not read on Fig. 6A, but is read on Figs. 6B and 6D;
Claim 10 reciting a second connection chip and a third chip (e.g., elements 22 and 21, respectively, in some figures of the application) is read on Figs. 9 and 10, note on Fig. 6A. Please, note that the current application is specific in language and identifications, and, in spite of nine chips disposed over conductive columns 14 in Figs. 6A-6D - paragraph 0178 of the published application US 2024/0178187 teaches that these figures have “a plurality of first connection chips 13 and a plurality of pairs of the first chip 11 and the second chip 12”. As is well-known, during examination, claims shall be read in view of the specification.
With respect to the amendment, please be reminded that the current application does not teach a single structure comprising such combination of elements as a ring and a heat dissipating lid as current Claim 8 implies – currently Claim 8, in view of the amended Claim 1, shall be rejected under both – 112(a) and 112(b).
In addition, a single structure comprised a ring (of the amended Claim 1) and a third packaging layer (as Claim 9 claims, in view of dependency o Claim 9 on Claim 1) exists in Species of Fig. 6D, not in Species of Fig. 6A. However, in order to speed up the prosecution of the application, and since a structure of Fig. 6D exists in the prior arts used for Claims 1-3, the current Office Action examines two Species of Fig. 6A and Fig. 6B – together.
Status of Claims
Claims 8, 10, and 12-20 are withdrawn from further consideration as being drawn to nonelected inventions.
Claims 1-6, 9, and 11 are examined on merits herein.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-6, 9, and 11 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 1: Lines 6 and 9-10 of Claim 1 recite: “the conductive columns”. The recitation is unclear since leads to a question: Which conductive columns of “a plurality of conductive columns” (cited by line 5) are cited with article “the”?
Appropriate correction is required.
For this Office Action, mainly due to use of the citation: “conductive columns” by Claim 2, the recitations of line 5 was interpreted as: “conductive columns”, in which case, lines 6 and 9-10 were interpreted as filed.
In re Claim 5: Claim 5 recites: “the plurality of conductive columns”. In view of the current interpretation of Claim 1, the cited recitation of Claim 5 was interpreted as: “the conductive columns”.
In re Claims 2-4, 6, 9, and 11: Claims 2-4, 6, 9, and 11 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as the claims are understood, Claims 1-6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0098421) in view of Jeng et al. (US 2020/0027837).
In re Claim 1, Wu teaches a chip package structure, comprising (Fig. 1F and 2):
a substrate 110 (called first redistribution structure, paragraph 0025);
a first connection chip 130 (paragraph 0025), disposed on a first surface of the substrate 110 (the first surface being a top surface), wherein an active surface 130a (which is used for connection of 130 to other dies, paragraph 0028) of the first connection chip 130 is away from the substrate 110;
a plurality of conductive columns 120 (paragraph 0020), disposed on the first surface of the substrate 110 and located on a periphery of the first connection chip 130 (note that the current Office Action interpreted “a periphery” based on the language of the current application, not on a common use of the word - which means an edge of an element and not located “nearby”), wherein
the conductive columns 120 are directly coupled to the substrate 110 (as being electroplated or deposited onto the substrate, paragraphs 0025-0026);
a first packaging layer 140 (paragraph 0031), disposed on the first surface of the substrate 110 and wrapping a side surface of the first connection chip 130 and side surfaces of the conductive columns 120, with top surfaces of the conductive columns 120 exposed;
a first chip 200A (paragraph 0038) disposed on a side, that is of the first packaging layer 140 and that is away from the substrate 110, and coupled to the first connection chip 130 (paragraph 0050, Claim 6); and
a second chip 200B (paragraph 0038) disposed on the side, that is of the first packaging layer 140 and that is away from the substrate 110, and coupled to both the conductive columns 120 (as shown in Fig. 7) and the first connection chip 130 (paragraph 0050, Claim 6); and
a ring 220 (paragraph 0044) disposed on the first surface of the substrate 110 and surrounding the first packaging layer.
In the embodiment of Fig. 1F, the first packaging layer 140 does not expose the active surface of the first connection chip 130, as Claim 1 claims and the first and second chips are not shown as being coupled to the conductive columns. However, in an embodiment of Fig. 7, the first packaging layer 140 exposes not only top surfaces of the conductive columns, but also an active surface of a connection chip 530 (paragraph 0074) and the first and second semiconductor chips 200A and 200B are shown as being coupled to the conductive columns 120.
In view of Fig. 7, it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify Fig. 1F by substituting its first connection chip having an active surface covered with the first packaging layer – with the connection chip having an active surface exposed from the first packaging layer (with corresponding modification of connections to the first and second chips), and to create coupling between the first and second semiconductor chips with the conductive columns, if such first connection chip and such electrical connections of the first and second chips are preferred for the manufacturer. In addition, see MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
Wu does not teach a ring disposed on the first surface of the substrate and surrounding the first packaging layer.
Jeng teaches (Figs. 1F and 2) a ring 270 (paragraph 0065) disposed on a first surface of substrate 260 (paragraph 0065) and extending from the first surface of the substrate 260 to a first chip 142 (paragraph 0021).
Wu and Jeng teach analogous arts directed to a chip package comprised a few chips disposed on a substrate through at least one redistribution layer, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Wu structure in view of the Jeng structure, since they are from the same field of endeavor, and the Jeng structure successfully functions.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Wu structure by disposing the ring on the first surface of the substrate and extending up to the first chip (per Jeng), obviously creating by that the ring surrounding the first packaging layer (of Wu), wherein such modification allows to reduce a warpage of the substrate during the structure manufacturing (Jeng, paragraph 0065).
In re Claim 2, Wu/Jeng teaches the chip package structure according to Claim 1 as cited above.
Wu/Jeng further teaches (Wu, Fig. 1F, paragraphs 0033) that the chip package structure also comprises a redistribution layer 150 disposed between the first packaging layer 140 and the first chip 200A; and the redistribution layer 150 is coupled to the conductive columns 120 and the first connection chip 130, and is further coupled to the first chip 200A and the second chip 200b (paragraph 0037 and as shown in Fig. 1F).
In re Claim 3, Wu/Jeng teaches the chip package structure according to Claim 1, wherein (Wu, Fig. 1F) a back surface of the first connection chip 130 is bonded to the substrate 110 – through a die attach film (Wu, paragraph 0028).
In re Claim 4, Wu/Jeng teaches the structure of Claim 1 as cited above, including the first connection chip (inherently comprising a back surface) and the substrate, with the first connection chip 130 coupled to the substrate 110 (Wu, Fig. 1F, paragraph 0037).
In the embodiment of Fig. 1F, Wu does not teach that the first connection chip comprises via that penetrate a back surface of this chip and are coupled to the substrate. But in the embodiment of Figs. 5, Wu teaches a first connection chip 430 comprising vias 434 that penetrate a back surface of chip 430 and are coupled to the substrate 110 (paragraphs 0062-0064).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Wu/Jeng structure of Claim 1 by substituting its first connection chip coupled to the substrate using only its pad with the first connection chip of Figs. 5 comprised vias penetrating its back surface to be coupled to with the substrate, if the first connection chip of this design is preferred for the manufacturer. In addition, see MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 5, Wu/Jeng teaches the chip package structure according to Claim 1 as cited above.
Wu further teaches (Fig. 1F, paragraph 0032) that heights of the plurality of conductive columns 120 are the same in a direction perpendicular to the substrate.
In re Claim 6, Wu/Jeng teaches the chip package structure according to Claim 1 as cited above.
Wu further teaches (Fig. 1F) that the chip package structure further comprises a second packaging layer 210 (paragraph 0042); and the second packaging layer 210 is disposed on the first packaging layer 140 and wraps at least a side surface of the first chip 200A and a side surface of the second chip 200b.
In re Claim 9, Wu/Jeng teaches the chip package structure according to Claim 1 as cited above.
Wu does not teach that the chip package structure further comprises a third packaging layer disposed on the first surface of the substrate and wrapping at least the side surface of the first chip, the side surface of the second chip, and the first packaging layer.
Jeng teaches a third packaging layer 290 (paragraph 0067), a portion of which is disposed on a first surface of substrate 260 and extends to a top of a first chip 142 (the number is shown in Fig. 1F), the ring 270 being disposed in the third packaging layer.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Wu/Jeng structure of Claim 1 by adding into the structure the third packaging layer of Jeng, which would wrap at least a side surface of the first chip, the side surface of the second chip, and the first packaging layer, when it is desirable to create a structure, including the ring, protected from inaccurate handling.
As far as the claims are understood, Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wu/Jeng in view of Hung et al. (US 2018/0025992).
In re Claim 11, Wu/Jeng teaches the chip package structure according to Claim 1 as cited above, and further teaches a second surface of the substrate as a back surface which is opposite to the first surface of the substrate.
Wu/Jeng does not teach that the chip package structure further comprises a fourth chip disposed on the second surface of the substrate.
Hung teaches (Fig. 55, paragraph 0038) a fourth chip 88 disposed on a second side of a substrate 60.
Wu/Jeng and Hung teach analogous arts directed to a package comprised chips and redistribution layers disposed over a substrate (comprised at least wiring), and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Wu/Jeng structure in view of the Hung structure since they are from the same filed of endeavor, and Hung created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Wu/Jeng structure of Claim 1 by adding a fourth chip disposed on the second side of the substrate, wherein it is desirable to have this chip structure operatively connected to other chips existing in the package (Hung, paragraph 0038).
.
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Lynne Gurley can be reached on 571-272-1670.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440.
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 06/20/26
Prosecution Insights