DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 and 19 have been amended.
Claim 16 is cancelled.
Claims 1, 3, 4, 8, 9, 11-15, and 19 have been examined.
The claim objections in the previous Office Action have been addressed and are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 8, 11-15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2010/0049961 by Bell et al. (hereinafter referred to as “Bell”) in view of US Publication No. 2021/0126877 by Jalal et al. (hereinafter referred to as “Jalal”) in view of US Patent No. 10, 133,599 by Sandstrom (hereinafter referred to as “Sandstrom”).
Regarding claims 1 and 19, taking claim 1 as representative, Bell discloses:
a data processing system comprising: a plurality of modular processing tiles distributed across more than one processing resource, each of the plurality of modular processing tiles comprising runtime-configurable processing circuitry (Bell discloses, at Figure 1 and related description, processing units, which discloses modular processing tiles distributed across more than one processing resource, that each include, as disclosed at Figure 2 and related description, programmable circuitry.); and
a control module to centrally control the plurality of modular processing tiles over a communication network and to access …[an external processing resource] through said communication network, said control module comprising (Bell discloses, at Figure 2 and related description, a function manager that reprograms the cores and that is coupled to cores, which discloses a control module to centrally control the plurality of modular processing tiles. As disclosed at Figure 1 and related description, the processing units are coupled to other components, e.g., additional processing resources, via an interconnect, which discloses a communication network.):
instruction decoding circuitry to decode instructions (Bell discloses, at Figure 1 and related description, the single thread optimization module provides instructions, which, given that the cores can be implemented as PowerPC cores, discloses decoding circuitry to decode the instructions.);
information collecting circuitry to collect information relating to said plurality of modular processing tiles …wherein said information relating to the plurality of modular processing tiles comprises tile telemetry of said plurality of modular processing tiles… (Bell discloses, at Figure 1 and related description, the single thread optimization module collects performance monitor information. Bell also discloses, at Figure 2 and related description, collecting performance data, which discloses tile telemetry.); and
instruction processing circuitry to process instructions decoded by the instruction decoding circuitry (Bell discloses, at Figure 2 and related description, core units, which discloses instruction processing circuitry to process instructions decoded by the instruction decoding circuitry.),
wherein, in response to an instruction to perform a processing task decoded by said instruction decoding circuitry, said instruction processing circuitry of said control module is configured to arbitrate said processing task between said…[external processing resource] and said at least a portion of said plurality of modular processing tiles based on one or more parameters (Bell discloses, at Figure 2 and related description, selecting which execution unit of a set of execution units should perform a given function, where the set can include additional (external) processing groups, as indicated at ¶ [0018], which discloses arbitration based on parameters.);
wherein, when said at least a portion of said plurality of modular processing tiles is selected in arbitration, said instruction processing circuitry is configured to generate …[configuration information] for at least a portion of said plurality of modular processing tiles based on the collected information relating to said portion of said plurality of modular processing tiles…(Bell discloses, at Figure 2 and related description, dynamically reprogramming core units based on measured workload activity, which discloses generating configuration information based on collected information. The workload activity is performed in response to an instruction to perform a processing task based on an instruction decoded by the decoding circuitry.), and
wherein, responsive to said …[configuration information], said runtime-configurable processing circuitry of said portion of said plurality of modular processing tiles is configured at runtime into an interconnected network to perform said processing task (Bell discloses, at Figure 2 and related description, dynamically reprogramming core units, which are coupled together, based on measured performance data, which discloses responsive to said …[configuration information], the control module is configured to, at runtime, select, arrange and functionally combine said portion of said plurality of modular processing tiles into an arrangement which discloses interconnected network to perform said processing task).
Bell does not explicitly disclose the aforementioned external processing resource is a cloud processing resource, the aforementioned collected information includes information relating to said communication network, said information relating to said communication network comprises network telemetry, the aforementioned configuration information is a configuration instruction, and the aforementioned configuration information is further based on the collected information relating to said communication network.
However, Bell discloses reprogramming core units based on performance monitoring information analyzed by a thread optimization module. See ¶ [0020] et seq. Bell also discloses implementing the thread optimization module as executable instructions. Given this disclosure, it would have been obvious to a person having ordinary skill in the art to implement the configuration information used to reconfigure the core units as a configuration instruction. Doing would improve performance by implementing a simple and direct approach to convey reconfiguration operations.
Also in the same field of endeavor (e.g., processing) Sandstrom discloses:
cloud computing (Sandstrom disclose, at col. 1, lines 34-49, cloud computing.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Bell to include cloud computing, as disclosed by Sandstrom, in order to effectively support high performance parallel computing. See Sandstrom, Id.
Also in the same field of endeavor (e.g., processing using interconnected elements) Jalal discloses:
detecting information related to an interconnect fabric and modifying operation in response to the information (Jalal discloses, at ¶ [0042], determining whether an interconnect fabric is congested, which discloses collecting information that includes information relating to said communication network and comprises network telemetry. Jalal also discloses, at ¶ [0042], performing different actions based on the collected information, which discloses configuration based on the collected information relating to said communication network.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Bell to include the collecting network information and configuring based on the network information, as disclosed by Jalal, in order to ensure efficient transmission of data between interconnected elements of a computing system.
Regarding claim 3, Bell discloses the elements of claim 2, as discussed above. Bell also discloses:
said tile telemetry comprises performance statistics of said plurality of modular processing tiles, said performance statistics being statistics relating to performance or power status of said modular processing tile, and, optionally, said performance statistics comprises power availability, memory availability, processing capacity, processing speed, processing latency, or any combination thereof (Bell discloses, at Figure 2 and related description, the performance data includes load data, which discloses processing capacity.).
Regarding claim 4, Bell discloses the elements of claim 1, as discussed above. Bell also discloses:
said plurality of modular processing tiles comprises local storage to store one or more past configurations of said runtime-configurable processing circuitry, and said information relating to plurality of modular processing tiles comprises said one or more past configurations (Bell discloses, at Figure 2 and related description, the processors store performance history, which discloses past configurations.).
Regarding claim 8, Bell discloses the elements of claim 1, as discussed above. Bell also discloses:
said at least a portion of said plurality of modular processing tiles forming said interconnected network is configured …in response to said configuration … [information] (Bell discloses, at Figure 2 and related description, configuring the processors, which discloses in response to a configuration instruction.).
Bell does not explicitly disclose the configuration comprises one or more cortical columns and the aforementioned configuration information is a configuration instruction. However, Bell discloses reprogramming core units based on performance monitoring information analyzed by a thread optimization module. See ¶ [0020] et seq. Bell also discloses implementing the thread optimization module as executable instructions. Given this disclosure, it would have been obvious to a person having ordinary skill in the art to implement the configuration information used to reconfigure the core units as a configuration instruction. Doing would improve performance by implementing a simple and direct approach to convey reconfiguration operations.
Also in the same field of endeavor (e.g., processing) Sandstrom discloses:
columns of processing elements (Sandstrom discloses, at Figure 5 and related description, columns of processing elements.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Bell to include connecting processing elements in columns, as disclosed by Sandstrom, in order to improve performance by efficiently using multiple processing elements.
Regarding claim 11, Bell discloses the elements of claim 1, as discussed above. Bell also discloses:
said network telemetry comprises bandwidth availability, network latency, network congestion, queue utilization, planned tasks, or any combination thereof.
However, in the same field of endeavor (e.g., processing using interconnected elements) Jalal discloses:
detecting congestion of an interconnect fabric (Jalal discloses, at ¶ [0042], determining whether an interconnect fabric is congested, which discloses network congestion.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Bell to include the collecting network information and configuring based on the network information, as disclosed by Jalal, in order to ensure efficient transmission of data between interconnected elements of a computing system.
Regarding claim 12, Bell discloses the elements of claim 1, as discussed above. Bell also discloses disclose:
said instruction processing circuitry is configured to generate said configuration …[information] further based on statistics on past task executions, one or more workload sub-classes, one or more hardware sub-classes, one or more cost models, one or more service priorities, one or more task priorities, a content resolution or a range of content resolution, or any combination thereof (Bell discloses, at Figure 2 and related description, the processors store performance history, which discloses statistics on past performance and using the history to generate configuration information.).
Bell does not explicitly disclose the aforementioned configuration information is a configuration instruction. However, Bell discloses reprogramming core units based on performance monitoring information analyzed by a thread optimization module. See ¶ [0020] et seq. Bell also discloses implementing the thread optimization module as executable instructions. Given this disclosure, it would have been obvious to a person having ordinary skill in the art to implement the configuration information used to reconfigure the core units as a configuration instruction. Doing would improve performance by implementing a simple and direct approach to convey reconfiguration operations.
Regarding claim 13, Bell discloses the elements of claim 1, as discussed above. Bell also discloses:
said instruction processing circuitry of said control module is configured to generate said configuration …[information] to select said at least a portion of said plurality of modular processing tiles from said plurality of modular processing tile to arrange said interconnected network based on a current workload of each of said at least a portion of said plurality of modular processing tiles (Bell discloses, at Figure 2 and related description, configuring the processors based on utilization, i.e., workload.).
Bell does not explicitly disclose the aforementioned configuration information is a configuration instruction. However, Bell discloses reprogramming core units based on performance monitoring information analyzed by a thread optimization module. See ¶ [0020] et seq. Bell also discloses implementing the thread optimization module as executable instructions. Given this disclosure, it would have been obvious to a person having ordinary skill in the art to implement the configuration information used to reconfigure the core units as a configuration instruction. Doing would improve performance by implementing a simple and direct approach to convey reconfiguration operations.
Regarding claim 14, Bell discloses the elements of claim 1, as discussed above. Bell also discloses:
said control module and said plurality of modular processing tiles are local to a single processing resource (Bell discloses, at Figure 1 and related description, the system includes the single thread optimization module and the processors, which discloses being local to a single processing resource.).
Regarding claim 15, Bell discloses the elements of claim 14, as discussed above. Bell also discloses:
a plurality of said processing resources and a global control module communicating with said plurality of processing resources over a communication network, said global control module being configured to centrally control said plurality of modular processing tiles of each processing resource through said control module of each processing resource (Bell discloses, at Figure 1 and related description, multiple processors, and a hypervisor that controls the system.).
Claims 1, 3, 4, 8, 9, 11-15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bell in view of Sandstrom in view of Jalal in view of in view of US Patent No.7,346,759 by Ansari et al. (previously cited and hereinafter referred to as “Ansari”).
Regarding claim 9, Bell discloses the elements of claim 8, as discussed above. Bell also discloses:
said at least a portion of said plurality of modular processing tiles forming said interconnected network is configured to aggregate …in response to said configuration … [information] (Bell discloses, at Figure 1 and related description, configuring the processors to work together, which discloses aggregating in response to a configuration instruction.).
Bell does not explicitly disclose aggregating the processors into a cascade such that one or more modular processing tiles of said interconnected network output directly to one or more other modular processing tiles of said interconnected network and the aforementioned configuration information is a configuration instruction.
However, Bell discloses reprogramming core units based on performance monitoring information analyzed by a thread optimization module. See ¶ [0020] et seq. Bell also discloses implementing the thread optimization module as executable instructions. Given this disclosure, it would have been obvious to a person having ordinary skill in the art to implement the configuration information used to reconfigure the core units as a configuration instruction. Doing would improve performance by implementing a simple and direct approach to convey reconfiguration operations.
Also in the same field of endeavor (e.g., processing using interconnected elements) Ansari discloses:
transmitting between adjacent elements (Ansari discloses, at Figures 28 and 29 and related description, transmitting data between adjacent processing elements.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Bell to include transmitting data between processing elements, as disclosed by Ansari, in order to improve performance by efficiently using multiple processing elements.
Response to Arguments
On pages 8-9 of the response filed May 21, 2026 (“response”), the Applicant argues, Applicant submits that the reconfiguring of Bell does not constitute arbitrating processing tasks, as claimed in the amended independent claims 1 and 19. Merriam-Webster defines arbitrate as "to act as arbiter [a person with power to decide a dispute] upon (a disputed question)". (See https://www.merriam-webster.com/dictionary/arbitrate and https://www.merriam-webster.com/dictionary/arbiter ). Thus, Applicant submits that it has not been shown that Bell teaches, discloses or suggests any deciding of a dispute, e.g., via distribution of a processing task between processors, as it instead discloses reconfiguring one processor for optimal performance. Thus, the reconfiguring of a processor for optimal performance of Bell does not fall within a normal dictionary definition of arbitrating. Further, page 11 lines 4-10 of Applicant's instant application as filed makes clear that 'arbitrating' is intended to mean selecting one of a plurality of recipients/processing means for a processing task, which is congruent with the dictionary definition. Applicant submits that Bell's reconfiguring discloses no selection of one of at least two choices of recipient for a processing task because the reconfiguring by default comprises adapting a single processor and not selecting between a plurality of processors to process a processing task. Thus, Applicant submits that Bell does not disclose, teach or suggest arbitration within the meaning of the amended independent claims.”
Though fully considered, the Examiner respectfully disagrees. The broadest reasonable interpretation of “arbitrating” in the context of this application is “selecting.” This is supported by the Applicant’s arguments stating, “Applicant's instant application as filed makes clear that 'arbitrating' is intended to mean selecting.” Despite the dictionary definition including a dispute, neither the claims nor specification disclose any sort of dispute, such as contention or any of the other types of disputes common in the computing arts.
The Examiner maintains that Bell discloses selecting which processing units to use. Selecting is practically inherent in using a particular processing unit. That is, unless the controller selects the processing unit, the processing unit cannot be used. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 9 of the response the Applicant argues, “Turning now to Seshadri, Applicant submits that this reference also does not teach, suggest, or disclose arbitrating within the meanings discussed above. Indeed, Seshadri's disclosure of cloud computing is made in passing (one reference in paragraph [0016]) and is not made with any suggestion of arbitration of processing tasks. Paragraph [0016] of Seshadri discusses a user device 20 and a server 30 but is silent on the subject of arbitration between them. Moreover, Seshadri is concerned with processing queries by configuring filters within a field programmable gate array according to reconfiguration bitstreams comprising filter properties associated with sub-queries (abstract). Like Bell, Seshadri contemplates reconfiguring a processor rather than arbitrating between a plurality of processing task recipients. Thus, Seshadri also does not disclose, teach or suggest arbitration within the meaning of the amended independent claims and does not remedy the deficiency of Bell in respect of original claim 17. Applicant accordingly submits that neither Bell nor Seshadri discloses, teaches or suggestion, alone or in combination, a system that arbitrates between processing a task locally versus sending it to an external resource. Nor do Bell or Seshadri teach, suggest, or disclose any hybrid architecture where a local system interacts with a separate, external cloud processing resource. Thus, no dynamic offloading is disclosed or rendered obvious by either reference, whether considered alone or in combination.”
Though fully considered, the Examiner respectfully disagrees. To the extent that the Applicant’s arguments reference Seshadri, the Examiner notes that Seshardri is not currently used in rejecting the Applicant’s claims.
Regarding cloud computing, the Examiner notes that Bell discloses, e.g., at ¶ [0018], interconnecting additional processor groups. These external additional processor groups arguably teach cloud processing resources, considering the breadth with which cloud processing resources are discussed in the current application. However, in order to expedite prosecution, the Examiner cites to Sandstrom, which explicitly discloses cloud computing, and the benefits thereof, at column 1. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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