DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Newly submitted claim 22 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
This application contains claims directed to the following patentably distinct species
Species A. Claim 8 wherein the metal blocks overlap with the TSV.
Species B. Claim 22 wherein the metal blocks have no overlap with the TSV. The species are independent or distinct because The position of the metal blocks are mutually exclusive. In addition, these species are not obvious variants of each other based on the current record.
Applicant is required under 35 U.S.C. 121 to elect a single disclosed species, or a single grouping of patentably indistinct species, for prosecution on the merits to which the claims shall be restricted if no generic claim is finally held to be allowable. Currently, claim 1 is generic.
There is a serious search and/or examination burden for the patentably distinct species as set forth above because at least the following reason(s) apply: The claims require at least different keyword searches.
Should applicant traverse on the ground that the species, or groupings of patentably indistinct species from which election is required, are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing them to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the species unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other species.
Upon the allowance of a generic claim, applicant will be entitled to consideration of claims to additional species which depend from or otherwise require all the limitations of an allowable generic claim as provided by 37 CFR 1.141.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 22 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Information Disclosure Statement
It is noted there is a copending PCT application with what appears to be a search report in the copending application which has not been supplied in the instant of applications. Further this makes the citations of CN 112470270 109427702 112534574 problematic since the ISR relies on specifics of the disclosure and not the abstract but only the abstract is provided. Applicant is reminded:
The concise explanation may indicate that a particular figure or paragraph of the patent or publication is relevant to the claimed invention. It might be a simple statement pointing to similarities between the item of information and the claimed invention. It is permissible but not necessary to discuss differences between the cited information and the claims. However, see Semiconductor Energy Laboratory Co. v. Samsung Electronics Co., 204 F.3d 1368, 1376, 54 USPQ2d 1001, 1007 (Fed. Cir. 2000) (“[A]lthough MPEP Section 609A(3) allows the applicant some discretion in the manner in which it phrases its concise explanation, it nowhere authorizes the applicant to intentionally omit altogether key teachings of the reference.”).
In Semiconductor Energy Laboratory, patentee during prosecution submitted an untranslated 29-page Japanese reference as well as a concise explanation of its relevance and an existing one-page partial English translation, both of which were directed to less material portions of the reference. The untranslated portions of the Japanese reference “contained a more complete combination of the elements claimed [in the patent] than anything else before the PTO.” 204 F.3d at 1376, 54 USPQ2d at 1005. The patentee, whose native language was Japanese, was held to have understood the materiality of the reference. “The duty of candor does not require that the applicant translate every foreign reference, but only that the applicant refrain from submitting partial translations and concise explanations that it knows will misdirect the examiner’s attention from the reference’s relevant teaching.” 204 F.3d at 1378, 54 USPQ2d at 1008.
Although a concise explanation of the relevance of the information is not required for English language information, applicants are encouraged to provide a concise explanation of why the English-language information is being submitted and how it is understood to be relevant. Concise explanations (especially those which point out the relevant pages and lines) are helpful to the Office, particularly where documents are lengthy and complex and applicant is aware of a section that is highly relevant to patentability or where a large number of documents are submitted and applicant is aware that one or more are highly relevant to patentability.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: Through substrate via lack antecedent basis; applicant only recites through silicon vias. Further claim 21 recitation of wherein at least some of the first bonding metal sub-blocks are electrically isolated from the first through substrate vias is not provided applicant only states wherein at least some of the first bonding metal blocks are electrically coupled to the first through silicon vias, however this is already stated in claims 1 13 and 18.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4 and 6-19 and 21 -22 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
a. With respect to claims 1, 14 and 18, applicant’s disclosure only supports through silicon vias there is no discussion of a generic through substrate via; TSV within the specification is explicitly defined as a through silicon via (paragraph 4) and every other place discusses only through silicon vias.
b. As to claim 21, recitation of wherein at least some of the first bonding metal sub-blocks are electrically isolated from the first through substrate vias.
Applicant’s claims have already stated wherein at least some of the first bonding metal blocks are electrically coupled to the first through silicon substrate vias further the specification only provides at least some of the first bonding metal blocks are electrically connected to the first through silicon vias and the first redistribution layer respectively.
Thus, in a stringent test the words do not appear in the specification. Further to what degree are they isolated at least some of the metal blocks are electrically connected in a capacitive manner. Applicant does not explain what is meant by at least some of the first bonding metal blocks are electrically connected to the first through silicon vias and the first redistribution layer respectively. And applicant provides no electrical circuit diagram for the blocks. Further the figures only show a cut away of the device and do not describe other connection outside of the plane. Thus, applicant does not have support for the recitation of wherein at least some of the first bonding metal sub-blocks are electrically isolated from the first through substrate vias.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The scope of wherein at least some of the first bonding metal sub-blocks are electrically isolated from the first through substrate vias is not clear the elements as depicted are at least in capacitive electrical communication so they are not totally electrically isolated from one another. Applicant recitation in the specification states: at least some of the first bonding metal sub-blocks are electrically connected to the first through silicon vias; and forming a second dielectric sub-layer and a plurality of second bonding metal sub-blocks on the first redistribution layer but does not indicate what this means with respect to isolation the office will take wherein at least some of the first bonding metal sub-blocks are electrically isolated from the first through substrate vias to be not directly electrically connected.
Claim(s) 1, 6-13, and 18 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lin 20210082846 (cited on ids).
a. As to claim 1 and 6, Lin teaches A chip stacked structure, comprising: a first chip comprising a first silicon substrate (figure 2L second or third chip up in stack of 20 item 10 of the set 20s; substrate shown figure 2J item 100); a first functional layer disposed on the first substrate (item 102 figure 2J); and, and first through substrate vias that penetrate the first substrate and the first functional layer (figure 2J item 110), and a wherein a first diameter of the first through silicon via close to the first functional layer is greater than a second diameter of the first through silicon via close to the first substrate (figure 2j and paragraph 14: The present disclosure is not limited to an amount of the through substrate vias 110. In some embodiments, the through substrate vias 110 extend along a thickness direction of the current structure from an exposed surface of the interconnection structure 104 (also referred as a front surface 1040 into the semiconductor substrate 100 through the interconnection structure 104 and the device layer 102. In these embodiments, the through substrate vias 110 may be tapered along their extending direction); a second chip (figure 2L topmost or third chip item 10 in the stack directly adjacent the third chip), wherein the second chip comprises comprising: a second substrate (item 100 figures 2L and 2J); and a second functional layer disposed on the second substrate and comprising a first side principle side away from the second substrate (figures 2J items 102 of the corresponding chip figure 2L side closest to 104 is away); a first redistribution layer disposed on the first side ( item 104 or item 114); and a first dielectric layer disposed between the first substrate and the first redistribution layer ( item 116 and 124); and a plurality of first bonding metal blocks disposed in the first dielectric layer ( items 122), wherein at least some of the first bonding metal blocks are electrically connected coupled to the first through silicon vias and the first redistribution layer respectively (figure 2L items 110 are connected to layer 122 in item 124), and wherein the first chip and the second chip are bonded through the first dielectric layer and the first bonding metal blocks (paragraph 26 n some embodiments, the semiconductor structures 10 in the same semiconductor structure 20 are bonded with one another by a hybrid bonding manner. As such, the passivation layer 124 of the upper semiconductor structure 10 is bonded with the isolation layer 136 of the lower semiconductor structure 10, whereas the bonding pads 122 of the upper semiconductor structure 10 are bonded with the through substrate vias 110 of the lower semiconductor structure 10).
Lin further teaches a first dielectric sub-layer disposed close to the first substrate on the surface opposite to the functional layer and comprising a first surface located away from the first substrate (items 136 e.g. figure 2i and 2l corresponding to the first chip the top end figure 2l would be away from the first substrate), wherein the first bonding metal sub-block is disposed in the first dielectric sub-layer and is exposed on the first surface (see item 110 not covered by item 136) ; and a second dielectric sub-layer mutually bonded to the first dielectric sub-layer (item 124 and item 116 figures 2i and 2l of the second chip ponding paragraph 25 bonding of items 122 to 110 and items 136 to 124 ), disposed close to the first redistribution layer (figure 2i), and comprising a second surface located away from the first redistribution layer (bottom relative to figure 2l), wherein the second bonding metal sub-block is disposed in the second dielectric sub-layer, and is exposed on the second surface (see figure 2i that does not cover 122 figure 2i and 2l).
Contrary to the assertion of applicant item 110 has a part in the substrate and a part in 136 (see e.g. figure 2k item 110 item 136) applicant give no explanation and provides not limits that the metal block cannot be integrally connected to the TSV. Thus, contrary to applicant’s assertion Lin teaches the features of claims 1 and 6.
c. As to claim 7, Lin teaches wherein the first dielectric sub-layer comprises a plurality of first hybrid bonding vias (portion of item 110 in item 136) in a one-to-one correspondence with the first through silicon vias (by definition correspond), wherein the first bonding metal sub-blocks are electrically coupled to the first through silicon vias through the first hybrid bonding vias (the top parts of item 110b are connect to the parts of the through vias in 100 102 and 104 by the via portion in item 136), wherein the second dielectric sub-layer comprises a plurality of second hybrid bonding vias (item 118 in item 116 figure 2F), and wherein the second bonding metal sub-blocks are electrically coupled to the first redistribution layer through the second hybrid bonding vias (items 122 connected to item 114 and 112b).
d. As to claim 8, Since there is not specific definition of what is and is not a redistribution layer portions of item 104 close to 114 can be considered a redistribution layer since the layer distribute out signals (figure 2F). Thus, Lin teaches further comprising a second distribution layer disposed between the first substrate and the first dielectric layer (portions of item 104 close to item 114 figure 2f), and electrically coupled to the first through silicon vias and the first bonding metal blocks (figure 2f depict items 108 electrically coupled to items 110 and 122 figure 2f).
e. As to claim 9, Lin teaches wherein a projection of the first bonding metal blocks on the first chip has an overlapping area with the first through silicon vias (items 122 and 110b directly overlap with item 110 from a plan view).
f. As to claim 10, Lin teaches wherein the second chip further comprises second through vias that penetrate the second substrate (see items 110 in the second chip penetrating 100) and the second functional layer and that are electrically coupled to the first redistribution layer (see they are all interconnect and electrically coupled figure 2l), wherein a third diameter of the second through silicon via close to the second functional layer is greater than a fourth diameter of the second through silicon via close to the second substrate (figure 2f and paragraph 14 indicates a taper or decreasing diameter as it goes from one end of the substrate to the redistribution layer), and wherein the chip stacked structure further comprises: a third chip comprising(topmost chip of figure 2l): a third substrate (figure 2f item 100); and a third functional layer disposed on the third substrate (items 102) and comprising a second side located away from the third substrate (side of items 102 near item 114) ; a fourth redistribution layer disposed on the second side (item 114 and item 112); a second dielectric layer disposed between the second substrate and the fourth redistribution layer (item 124 or item 136 of the second chip); and a plurality of second bonding metal blocks disposed in the second dielectric layer (items 122 or portions of item 110 in the second chip), wherein at least some of the second bonding metal blocks are electrically coupled to the second through silicon vias and the fourth redistribution layer (see figure 2l and figure 2f).
g. As to claim 11, Lin teaches wherein the chips comprises: a third bonding metal sub-block disposed close to the second through silicon vias portion of (item 110b of the second chip figure 2l and 2j); and a fourth bonding metal sub-block (items 122 of the thirds chip) that are mutually bonded (items 122 to the third bonding metal sub-block and disposed close to the fourth redistribution layer (item 122 of the third chip is close to the fourth redistribution layer bonding described in paragraph 25).
h. As to claim 12, Lin teaches a third dielectric sub-layer disposed close to the second substrate and comprising a first surface located away from the second substrate (item 136 figures 2J and 2l), wherein the third bonding metal sub-block is disposed in the third dielectric sub-layer and is exposed on the first surface (items 110b surface near the top of item 136); and a fourth dielectric sub-layer disposed with the third dielectric sub-layer in a stacked manner (item 124), disposed close to the fourth redistribution layer (it is near items 114 and item 112), and comprising a second surface located away from the fourth redistribution layer (portion of item 124 away from the vias 110), wherein the fourth bonding metal sub-block is disposed in the fourth dielectric sub-layer, and is exposed on the second surface (items 122).
i. As to claim 13, Lin teaches wherein a projection of the second through silicon vias on the first chip has no overlapping area with the first through silicon vias (they directly overlap in a plan view per figures 2).
j. As to claim 18 Lin teaches As to claim 1, Lin teaches A chip stacked structure, comprising: a first chip comprising a first silicon substrate (figure 2L second or third chip up in stack of 20 item 10 of the set 20s; substrate shown figure 2J item 100); a first functional layer disposed on the first substrate (item 102 figure 2J); and, and first through substrate vias that penetrate the first substrate and the first functional layer (figure 2J item 110), and a wherein a first diameter of the first through silicon via close to the first functional layer is greater than a second diameter of the first through silicon via close to the first substrate (figure 2j and paragraph 14: The present disclosure is not limited to an amount of the through substrate vias 110. In some embodiments, the through substrate vias 110 extend along a thickness direction of the current structure from an exposed surface of the interconnection structure 104 (also referred as a front surface 1040 into the semiconductor substrate 100 through the interconnection structure 104 and the device layer 102. In these embodiments, the through substrate vias 110 may be tapered along their extending direction); a second chip (figure 2L topmost or third chip item 10 in the stack directly adjacent the third chip), wherein the second chip comprises comprising: a second substrate (item 100 figures 2L and 2J); and a second functional layer disposed on the second substrate and comprising a first side principle side away from the second substrate (figures 2J items 102 of the corresponding chip figure 2L side closest to 104 is away); a first redistribution layer disposed on the first side ( item 104 or item 114); and a first dielectric layer disposed between the first substrate and the first redistribution layer ( item 116 and 124); and a plurality of first bonding metal blocks disposed in the first dielectric layer ( items 122), wherein at least some of the first bonding metal blocks are electrically connected coupled to the first through silicon vias and the first redistribution layer respectively (figure 2L items 110 are connected to layer 122 in item 124), and wherein the first chip and the second chip are bonded through the first dielectric layer and the first bonding metal blocks (paragraph 26 n some embodiments, the semiconductor structures 10 in the same semiconductor structure 20 are bonded with one another by a hybrid bonding manner. As such, the passivation layer 124 of the upper semiconductor structure 10 is bonded with the isolation layer 136 of the lower semiconductor structure 10, whereas the bonding pads 122 of the upper semiconductor structure 10 are bonded with the through substrate vias 110 of the lower semiconductor structure 10).
Lin further teaches a printed circuit board (paragraph 26); and a chip stacked structure electrically coupled to the printed circuit board (paragraph 26 item 142 connect to the circuit board thus the chips are electrically connected to the printed circuit board).
Lin further teaches a first dielectric sub-layer disposed close to the first substrate on the surface opposite to the functional layer and comprising a first surface located away from the first substrate (items 136 e.g. figure 2i and 2l corresponding to the first chip the top end figure 2l would be away from the first substrate), wherein the first bonding metal sub-block is disposed in the first dielectric sub-layer and is exposed on the first surface (see item 110 not covered by item 136) ; and a second dielectric sub-layer mutually bonded to the first dielectric sub-layer (item 124 and item 116 figures 2i and 2l of the second chip ponding paragraph 25 bonding of items 122 to 110 and items 136 to 124 ), disposed close to the first redistribution layer (figure 2i), and comprising a second surface located away from the first redistribution layer (bottom relative to figure 2l), wherein the second bonding metal sub-block is disposed in the second dielectric sub-layer, and is exposed on the second surface (see figure 2i that does not cover 122 figure 2i and 2l)
Contrary to the assertion of applicant item 110 has a part in the substrate and a part in 136 (see e.g. figure 2k item 110 item 136) applicant give no explanation and provides not limits that the metal block cannot be integrally connected to the TSV. Thus, contrary to applicant’s assertion Lin teaches the features of claims 1 and 6.
It is noted without some structure of a printed circuit board item 132 can be a printed circuit board.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4,14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Wang (CN 101179037 cited on ids).
a. As to claims 2-3,, Lin teaches As to claim 1Lin teaches A chip stacked structure, comprising: a first chip comprising a first silicon substrate (figure 2L second or third chip up in stack of 20 item 10 of the set 20s; substrate shown figure 2J item 100); a first functional layer disposed on the first substrate (item 102 figure 2J); and, and first through substrate vias that penetrate the first substrate and the first functional layer (figure 2J item 110), and a wherein a first diameter of the first through silicon via close to the first functional layer is greater than a second diameter of the first through silicon via close to the first substrate (figure 2j and paragraph 14: The present disclosure is not limited to an amount of the through substrate vias 110. In some embodiments, the through substrate vias 110 extend along a thickness direction of the current structure from an exposed surface of the interconnection structure 104 (also referred as a front surface 1040 into the semiconductor substrate 100 through the interconnection structure 104 and the device layer 102. In these embodiments, the through substrate vias 110 may be tapered along their extending direction); a second chip (figure 2L topmost or third chip item 10 in the stack directly adjacent the third chip), wherein the second chip comprises comprising: a second substrate (item 100 figures 2L and 2J); and a second functional layer disposed on the second substrate and comprising a first side principle side away from the second substrate (figures 2J items 102 of the corresponding chip figure 2L side closest to 104 is away); a first redistribution layer disposed on the first side ( item 104 or item 114); and a first dielectric layer disposed between the first substrate and the first redistribution layer ( item 116 and 124); and a plurality of first bonding metal blocks disposed in the first dielectric layer ( items 122), wherein at least some of the first bonding metal blocks are electrically connected coupled to the first through silicon vias and the first redistribution layer respectively (figure 2L items 110 are connected to layer 122 in item 124), and wherein the first chip and the second chip are bonded through the first dielectric layer and the first bonding metal blocks (paragraph 26 n some embodiments, the semiconductor structures 10 in the same semiconductor structure 20 are bonded with one another by a hybrid bonding manner. As such, the passivation layer 124 of the upper semiconductor structure 10 is bonded with the isolation layer 136 of the lower semiconductor structure 10, whereas the bonding pads 122 of the upper semiconductor structure 10 are bonded with the through substrate vias 110 of the lower semiconductor structure 10).
Lin further teaches wherein each of the first through silicon vias comprises: an electroplated copper column comprising a side surface (item 110 have side surfaces directly adjacent to items 102 and 104, though electroplated is product by process Lin teaches forming item 110 by electroplating paragraph 14) and a first surface located away from the second chip ( the portion of the bottom part/wider surface away from the second chip). Lin further teaches wherein the electroplated column further comprises a second surface located close to the second chip, and wherein the first conductive barrier layer is not disposed on the second surface ( the surface of the via next to the second chip). Lin teaches a conductive barrier on the side surface.
Lin also teaches forming the barrier on the bottom surface thus Lin does not teach and a first conductive barrier layer wrapping the side surface and not disposed on the first surface (paragraph 15).
Wang teaches a first conductive barrier layer wrapping (item 15 fig. 8) a TSV (item 14/18 fig. 8 and 12 ) the side surface and not disposed on the top of the via or the bottom of the surface (item 15 is not on end facing the chips figure 11 and 12).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the barrier only on the sidewalls and not on the top and bottom surfaces of the through via since the structure would have worked in substantially the same manner and would have used less material for the barrier conserving the material for future processes.
b. As to claims 4 and 16, Lin teaches wherein the first conductive barrier layer comprises one or more of titanium, titanium nitride, tantalum, or tantalum nitride (paragraph 15).
c. As to claims 14-15, and 17 Lin teaches A chip stacked structure, comprising: a first chip comprising a first silicon substrate (figure 2L second or third chip up in stack of 20 item 10 of the set 20s; substrate shown figure 2J item 100); a first functional layer disposed on the first substrate (item 102 figure 2J); and, and first through substrate vias that penetrate the first substrate and the first functional layer (figure 2J item 110), and a wherein a first diameter of the first through silicon via close to the first functional layer is greater than a second diameter of the first through silicon via close to the first substrate (figure 2j and paragraph 14: The present disclosure is not limited to an amount of the through substrate vias 110. In some embodiments, the through substrate vias 110 extend along a thickness direction of the current structure from an exposed surface of the interconnection structure 104 (also referred as a front surface 1040 into the semiconductor substrate 100 through the interconnection structure 104 and the device layer 102. In these embodiments, the through substrate vias 110 may be tapered along their extending direction); a second chip (figure 2L topmost or third chip item 10 in the stack directly adjacent the third chip), wherein the second chip comprises comprising: a second substrate (item 100 figures 2L and 2J); and a second functional layer disposed on the second substrate and comprising a first side principle side away from the second substrate (figures 2J items 102 of the corresponding chip figure 2L side closest to 104 is away); a first redistribution layer disposed on the first side ( item 104 or item 114); and a first dielectric layer disposed between the first substrate and the first redistribution layer ( item 116 and 124); and a plurality of first bonding metal blocks disposed in the first dielectric layer ( items 122), wherein at least some of the first bonding metal blocks are electrically connected coupled to the first through silicon vias and the first redistribution layer respectively (figure 2L items 110 are connected to layer 122 in item 124), and wherein the first chip and the second chip are bonded through the first dielectric layer and the first bonding metal blocks (paragraph 26 n some embodiments, the semiconductor structures 10 in the same semiconductor structure 20 are bonded with one another by a hybrid bonding manner. As such, the passivation layer 124 of the upper semiconductor structure 10 is bonded with the isolation layer 136 of the lower semiconductor structure 10, whereas the bonding pads 122 of the upper semiconductor structure 10 are bonded with the through substrate vias 110 of the lower semiconductor structure 10).
Lin further teaches wherein each of the first through silicon vias comprises: an electroplated copper column comprising a side surface (item 110 have side surfaces directly adjacent to items 102 and 104, though electroplated is product by process Lin teaches forming item 110 by electroplating paragraph 14) and a first surface located away from the second chip ( the portion of the bottom part/wider surface away from the second chip). Lin further teaches wherein the electroplated column further comprises a second surface located close to the second chip, and wherein the first conductive barrier layer is not disposed on the second surface ( the surface of the via next to the second chip). Lin teaches a conductive barrier on the side surface.
Lin further teaches a first dielectric sub-layer disposed close to the first substrate on the surface opposite to the functional layer and comprising a first surface located away from the first substrate (items 136 e.g. figure 2i and 2l corresponding to the first chip the top end figure 2l would be away from the first substrate), wherein the first bonding metal sub-block is disposed in the first dielectric sub-layer and is exposed on the first surface (see item 110 not covered by item 136) ; and a second dielectric sub-layer mutually bonded to the first dielectric sub-layer (item 124 and item 116 figures 2i and 2l of the second chip ponding paragraph 25 bonding of items 122 to 110 and items 136 to 124 ), disposed close to the first redistribution layer (figure 2i), and comprising a second surface located away from the first redistribution layer (bottom relative to figure 2l), wherein the second bonding metal sub-block is disposed in the second dielectric sub-layer, and is exposed on the second surface (see figure 2i that does not cover 122 figure 2i and 2l)
Contrary to the assertion of applicant item 110 has a part in the substrate and a part in 136 (see e.g. figure 2k item 110 item 136) applicant give no explanation and provides not limits that the metal block cannot be integrally connected to the TSV. Thus, contrary to applicant’s assertion Lin teaches the features of claims 1 and 6.
Lin also teaches forming the barrier on the bottom surface thus Lin does not teach and a first conductive barrier layer wrapping the side surface and not disposed on the first surface (paragraph 15).
Wang teaches a first conductive barrier layer wrapping (item 15 fig. 8) a TSV (item 14/18 fig. 8 and 12 ) the side surface and not disposed on the top of the via or the bottom of the surface (item 15 is not on end facing the chips figure 11 and 12).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the barrier only on the sidewalls and not on the top and bottom surfaces of the through via since the structure would have worked in substantially the same manner and would have used less material for the barrier conserving the material for future processes.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Gao (20200013754).
a. As to claim 19, Lin teaches A manufacturing method, comprising: providing a substrate (item 110 figure 2b) forming first vias on a first chip from a first side of a first functional layer of the first chip (figure 2b items 110f in item 102); bonding a carrier and the first chip (figure 2g item 132), so that the first functional layer is closer to the carrier than the first substrate of the first chip (item 102 is closer to item 132 than 100 is) ; forming a first redistribution layer on a second functional layer of a second chip figure 2f item 112 and 114); bonding the first chip and the second chip (paragraph 25 and figure 2l); forming a first dielectric layer between the first substrate and the first redistribution layer (items 136 of the first chip figure 2I-2J); and forming a plurality of first bonding metal blocks located in the first dielectric layer (item 110b at the top of item 136), wherein so that at least some of the first bonding metal blocks after bonding are electrically connected to the first through silicon vias and the first redistribution layer (see figure 2l the portions 110b are connected).
It is not complete clear on the scope of forming a plurality of first bonding metal blocks located in the first dielectric layer assuming arguendo it cannot be simultaneous with the TSV Gao teaches form chips (item 102 figure 1) with TSV (item 114) with a dielectric (106s) on either side of the substrate (104) and forming a metal block separate from the TSV formation item 110).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to have formed a separate metal block in the dielectric to provide the desired metal composition to optimize the hybrid bonding between the first chip and the second chip.
Lin teaches wherein each of the first vias does not penetrate the first substrate (figure 2f and 2g); and, and wherein after the bonding the carrier and the first chip (figure 2g), and before bonding the first chip and the second chip, the manufacturing method further comprises thinning the first substrate from a second side that is of the first substrate and that is away from the first functional layer to expose the first through silicon vias (figure 2H exposes back ends of the vias are exposed to form TSVs).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Haba 20200227367 and CN 112470270B cited on IDs but only abstract is provided.
The office is not providing a translation of CN 112470270B since it was cited in the WIPO and specifically references paragraphs within the disclosure. Thus, the office must assume that applicant has access since it was provided to applicant in that office action. Further it appears that the reference is in applicant’s principal language. The office will provide explicit recitation from readily available machine translations.
Lin does not explicitly teach wherein at least some of the first bonding metal sub-blocks are electrically isolated from the first through substrate vias (sic not directly connected). It is noted it appears applicant is using the figures to preclude electrical connection between the TSV and the metal blocks however there is no discussion with the electrical connection in the specification.
Haba teaches providing pads on the front and back of the wafer die in dielectrics/bonding layer (figure 5-6 items 6 and 6b on the TSV item 13 through thinned item 2 dielectrics items 4a and 4b paragraphs 29)
Haba further teaches these pads can be in directly electrically connect to TSV or not associated (sic isolated from the TSV). As well as bonding multiple chips front to back figures 9.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide additional contacts in the front and back dielectrics some associated or electrically connected to the TSVs and others not associated or isolated/not directly connected to the TSV.
One would have been so motivated to use conventional contact patterns and structure to provide expected outcomes of connected dies with the desired interconnectivity.
Further assuming arguendo that it precludes any electrical contact CN 112470270 teaches forming dielectrics on the top and bottom of a substrate device (figure 1a 2 items 104 and 106 respectively).
‘270 recites The representative device die 102 may be formed using various techniques to include a base substrate 104 and one or more insulating or dielectric layers 106. The base substrate 104 may be composed of silicon, germanium, glass, quartz, a dielectric surface, a direct gap semiconductor material or layer, or an indirect gap semiconductor material or layer, or other suitable material. An insulating layer 106 is deposited or formed over the substrate 104 and may be made of materials such as oxides, nitrides, oxynitrides, oxycarbides, carbides, carbonitrides, diamond-like materials, glass, ceramicsInorganic dielectric material layers such as glass-ceramic, and the like.
CN ‘270 further teaches TSV 114:
Some embedded conductive features or interconnect structures may include metal pads 110 or conductive traces 112 that extend partially into the dielectric substrate 106 below the prepared surface 108. For example, some patterned metal (e.g., copper) features 110 or 112 may be about 0.5 to 2 microns thick. The metal of these features 110 or 112 may expand as the metal heats up during annealing. Other conductive interconnect structures may include metal (e.g., copper) Through Silicon Vias (TSVs) 114 or the like that extend partially through or completely through the substrate 102 orthogonal to the bonding surface 108 and that include a substantial amount of metal. For example, the TSV114 may extend about 50 microns, depending on the thickness of the substrate 102. The metal of the TSV114 may also expand when heated. The pads 110 and/or traces 112 may or may not be electrically coupled to the TSVs 114, as shown in fig. 1A.
CN’270 further teaches a plurality of conductive blocks some in electrical communication with the TSV and others not (figure 1a 2 items 110 with 112 items 110 being the blocks):
Some embedded conductive features or interconnect structures may include metal pads 110 or conductive traces 112 that extend partially into the dielectric substrate 106 below the prepared surface 108. For example, some patterned metal (e.g., copper) features 110 or 112 may be about 0.5 to 2 microns thick. The metal of these features 110 or 112 may expand as the metal heats up during annealing. Other conductive interconnect structures may include metal (e.g., copper) Through Silicon Vias (TSVs) 114 or the like that extend partially through or completely through the substrate 102 orthogonal to the bonding surface 108 and that include a substantial amount of metal. For example, the TSV114 may extend about 50 microns, depending on the thickness of the substrate 102. The metal of the TSV114 may also expand when heated. The pads 110 and/or traces 112 may or may not be electrically coupled to the TSVs 114, as shown in fig. 1A.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide additional metal blocks/ contacts in the dielectric item 136 or an additional dielectric with contacts on 136. Wherein some are electrically in contact with TSVV and others are not to use conventional hybrid bonding technique to provide expected out comes of improved bonding as suggest by ‘270:
The die or wafer may be bonded in a stacked arrangement using various bonding techniques, including direct dielectric bonding, non-adhesive techniques (such as ZiBond TM) Or hybrid bonding techniques (such as DBI TM ) Both of which are available from Invens as binding Technologies, Inc. (formerly Ziptronix, Inc.), Xperi Inc. Bonding involves spontaneous processes This spontaneous process occurs under ambient conditions when two prepared surfaces are brought together (see, e.g., U.S. patent nos. 6,864,585 and 7,485,968, the entire contents of which are incorporated herein by reference).
Response to Arguments
Applicant's arguments filed 7/14/2026 have been fully considered but they are not persuasive.
Applicant argues:
Lin, paragraphs 18 and 26 (emphasis added). The Office Action maps Lin's through-substrate via 110/110b to the claimed first bonding metal sub-block and maps bonding pad 122 to the claimed second bonding metal sub-block. However, Lin discloses bonding pad 122 directly bonded to through-substrate via 110. Thus, Lin teaches a pad-to-TSV bond, not a first bonding metal block comprising a first bonding metal sub-block bonded to a second bonding metal sub-block.
Furthermore, the present claims require a first bonding metal sub-block disposed in a first dielectric sub-layer and a second bonding metal sub-block disposed in a second dielectric sub-layer. In Lin, the alleged first bonding metal sub-block identified by the Examiner is the through-substrate via 110 itself, not a separate bonding metal sub-block disposed in dielectric layer 136. Accordingly, Lin does not disclose the claimed arrangement of bonded bonding metal sub-blocks disposed in respective dielectric sub-layers. As such, Lin fails to disclose that a first dielectric layer comprises a first dielectric sub-layer disposed on a side of the first substrate that is away from the first functional layer and a second dielectric sub-layer disposed on the first redistribution layer and bonded to the first dielectric sub-layer, wherein each of the first bonding metal blocks comprises a first bonding metal sub-block disposed in the first dielectric sub-layer and a second bonding metal sub-block disposed in the second dielectric sub-layer and bonded to the first bonding metal sub-block, as claimed. Thus, Lin fails to teach each and every element of independent claims 1 and 18, and consequently fails to anticipate claims 1, 6-13, and 18.
This is not found convincing 110 is not wholly in the substrate portions of the of 110 are in item 136. Further applicant has not precluded the metal blocks to be integrally formed with the TSVs. The office asserts that item 110 has a through via portion in the substrate and a metal block portion in the dielectric item 136. This is supported by the figures of Lin. Applicant does not address this interpretation. Further new claim 21 evidences that the metal blocks can be directly electrically connected in claims 1 14 and 18 since they now are clearly broader than new claim 21.
Additionally, with respect to claim 19, the Examiner asserts that Lin discloses similar limitations. See Office Action, pp. 14-15. Lin discloses through-substrate vias in a completed semiconductor structure, but Lin does not disclose claimed manufacturing sequence of (1) forming first vias from a first side of a first functional layer of a first chip into a first substrate of the first chip, wherein the first vias initially do not penetrate the first substrate; (2) bonding a carrier to the first chip such that the first functional layer faces the carrier; and (3) thinning the first substrate from a side opposite the first functional layer to expose the first vias and form first through substrate vias, as claimed. Gao fails to cure the deficiencies of Lin. Accordingly, claim 19 is patentable over Lin in view of Gao and is in condition for allowance.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Gao is specifically brought to provide a separate metal block formation as required by the method. Since the argument only address Lin, the argument cannot be found convincing. The office has already acknowledged Lin does not teach the steps of claim 19 singularly and used Gao to show obviousness. Since applicant does not address Gao applicant does not address the rejection of claim 19.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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