DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 07/14/2026. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 02/28/2024.
Oath/Declaration
The oath or declaration filed on 02/02/2024 is acceptable.
Election/Restrictions
Applicant’s election, without traverse, group I: corresponding to claims 12-20, in the “Response to Election / Restriction Filed” filed on 07/14/2026 is acknowledged. This office action considers claims 1-20 are thus pending for prosecution of which, non-elected claims 1-11 are withdrawn, and elected claims 12-20 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12-13, 17-18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chuang et al (US 2022/0406886 A1; hereafter Chuang).
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Regarding claim 12. Chuang discloses a semiconductor structure, comprising:
a substrate (Fig 3, annotated layers [ 163,165,167,169], construed as substrate), wherein the substrate (Fig 3, annotated substrate) includes a first side and a second side opposite to the first side (Fig 3, annotated substrate), and the substrate (Fig 3, annotated substrate) includes a first region (Fig 3, annotated substrate first region) and a second region (Fig 3, annotated substrate second region);
a device layer (device layer 155, Para [0056]) located over the first side of the first region, wherein the device layer (device layer 155, Para [0056]) includes a device structure (HVSD 115A, Para [0028]);
a first electrical connection structure (right side, metal interconnect structure 137 includes conductive lines 110 and vias 103, Para [ 0039]) located over the device layer (device layer 155, Para [0056]), wherein the first electrical connection structure (right side, metal interconnect structure 137 includes conductive lines 110 and vias 103 , Para [ 0039]) is electrically connected to the device structure (HVSD 115A, Para [0016, 0028]);
a second electrical connection structure (left side, metal interconnect structure 137 includes conductive lines 110 and vias 103, Para [0039]) located over the first side of the second region (left side, metal interconnect structure 137 includes conductive lines 110 and vias 103, Para [0039]);
a first connecting structure (right side TSV 139C, Para [0041]) located in the first region (right side TSV 139C, Para [0041]), wherein the first connecting structure (right side TSV 139C, Para [0041]) penetrates the substrate (Fig 3, annotated substrate) and is electrically connected to the device structure (HVSD 115A, Para [0028]);
a third electrical connection structure (pads 175A, Para [0065]) located on the second side of the first region (pads 175A, Para [0065], annotated first region), wherein the third electrical connection structure (pads 175A, Para [0065]) is electrically connected to the first connecting structure (right side TSV 139C, Para [0041]); and
a second connecting structure (left side TSV 139E, Para [ 0041, 0065], also shown in figure 1) located in the second region (Fig 3, annotated substrate second region), wherein the second connecting structure (left side TSV 139E, Para [ 0041, 0065], also shown in figure 1) is electrically connected ( via n-well, p-well and metal interconnect structure 137) to the third electrical connection structure (pads 175A, Para [ 0065]), the second connecting structure (left side TSV 139E, Para [ 0041, 0065], also shown in figure 1) extends from the second side of the substrate (Fig 3, annotated substrate) to the first side of the substrate (Fig 3, annotated substrate), the second connecting structure (left side TSV 139E, Para [ 0041, 0065], also shown in figure 1) penetrates the substrate (Fig 3, annotated substrate) and the device layer (device layer 155, Para [0056]), and the second connecting structure (left side TSV 139E, Para [ 0041, 0065], also shown in figure 1) is electrically connected to the second electrical connection structure (left side, metal interconnect structure 137 includes conductive lines 110 and vias 103, Para [0039]).
Regarding claim 13. Chuang discloses the semiconductor structure according to claim 12, wherein:
the device layer (device layer 155, Para [0056]) includes an isolation structure (deep trench isolation (DTI) structure 141, Para [ 0029]) and the device structure (HVSD 115A, Para [0016, 0028]) located within the isolation structure (deep trench isolation (DTI) structure 141, Para [ 0029]), wherein the device structure includes a transistor, a capacitor, or an inductor(HVSD 115A, Para [0016, 0028]); and the isolation structure (deep trench isolation (DTI) structure 141, Para [ 0029]) is also located over the first side of the second region (Fig 3, annotated substrate first and second region).
Regarding claim 17. Chuang discloses the semiconductor structure according to claim 12, Chuang further discloses wherein:
the first electrical connection structure (right side, metal interconnect structure 137 includes conductive lines 110 and vias 103, Para [ 0039]) includes a plurality of layers of first plugs and a plurality of layers of first metal layers (right side, metal interconnect structure 137 includes conductive lines 110 and vias 103, Para [ 0039]), and the plurality of layers of the first plugs and the plurality of layers of the first metal layers are alternately arranged (right side, metal interconnect structure 137 includes conductive lines 110 and vias 103, Para [ 0039]);
the second electrical connection structure (left side, metal interconnect structure 137 includes conductive lines 110 and vias 103, Para [0039]) includes a plurality of layers of second metal layers and a second plug located between second metal layers of the plurality of layers of second metal layers (left side, metal interconnect structure 137 includes conductive lines 110 and vias 103, Para [0039]); and the second connecting structure (left side, metal interconnect structure 137 includes conductive lines 110 and vias 103, Para [0039]) is electrically connected to a second metal layer of the plurality of layers of second metal layers (left side, metal interconnect structure 137 includes conductive lines 110 and vias 103, Para [0039]).
Regarding claim 18. Chuang discloses the semiconductor structure according to claim 12, Chuang further discloses wherein: the substrate (Fig 3, annotated layers [ 163,165,167,169], construed as substrate) includes a base (layer 169) and a fin structure (element 141, fin shaped) located over the base (layer 169).
Regarding claim 20. Chuang discloses the semiconductor structure according to claim 12, Chuang further discloses wherein: the first connecting structure (right side TSV 139C, Para [0041]) is made of a material including metal or metal nitride ( Para [ 0064]); the second connecting structure (left side TSV 139C, Para [0041]) is made of a material including metal or metal nitride ( Para [ 0064]); the metal includes copper, aluminum, tungsten, cobalt, nickel, tantalum, or a combination thereof ( Para [ 0064]); and the metal nitride includes tantalum nitride, titanium nitride, or a combination thereof ( Para [ 0064]).
Allowable Subject Matter
Claims 14-16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 14. a first dielectric structure located over the isolation structure, wherein the first electrical connection structure and the second electrical connection structure are located in the first dielectric structure; and a second dielectric structure located over the second side of the substrate, wherein the third electrical connection structure is located within the second dielectric structure, the second connecting structure penetrates the second dielectric structure, the substrate, the device layer, and part of the first dielectric structure.
Claim 15 is objected based on the dependency of claim 14.
Regarding claim 16. wherein: the third electrical connection structure includes a plurality of layers of third plugs and a plurality of layers of third metal layers, and the plurality of layers of the third plugs and the plurality of layers of the third metal layers are alternately arranged.
Regarding claim 19. wherein: the first connecting structure includes a first portion and a second portion in contact with the first portion; the first portion extends from the first side of the substrate to the second side of the substrate, a bottom of the first portion is located in the first region, and a top of the first portion is located in the device layer; and the second portion extends from the second side of the substrate to the first side of the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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