Prosecution Insights
Last updated: May 29, 2026
Application No. 18/431,112

SEMICONDUCTOR DEVICES

Non-Final OA §102§103
Filed
Feb 02, 2024
Priority
Mar 08, 2017 — CN 201710134782.1 +5 more
Examiner
PATEL, REEMA
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co. Ltd.
OA Round
4 (Non-Final)
89%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
980 granted / 1106 resolved
+20.6% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
30 currently pending
Career history
1149
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
61.9%
+21.9% vs TC avg
§102
10.4%
-29.6% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1106 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) were submitted on 7/8/25 and 7/28/25. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-5, 11-12, 15-17, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (U.S. 2016/0204117 A1; “Liu”). Regarding claim 1, Liu discloses a semiconductor device, comprising: A first stacked layer (second 142 from the bottom to uppermost 142, 131, Fig. 35A) ([0198]); An insulating layer (170 and bottommost 232, Fig. 35A) disposed over the first stacked layer ([0205]); A second stacked layer (second from the bottom 232 to uppermost 242, Fig. 35A) disposed over the insulating layer ([0222]); A channel structure (160, Fig. 35A) extending through the second stacked layer (second from the bottom 232 to uppermost 242, Fig. 35A), the insulating layer (170 and bottommost 232, Fig. 35A) and the first stacked layer (second 142 from the bottom to uppermost 142, 131, Fig. 35A), wherein the channel structure comprises: A first channel structure (160 within stack from second 142 to uppermost 142, 131, Fig. 35A) extending through the first stacked layer ([0242]); A second channel structure (160 within the stack comprising second from the bottom 232 to uppermost 242, Fig. 35A) extending through the second stacked layer ([0242]); and A third channel structure (160 within 170 and bottommost 232, Fig. 35A) disposed in the insulating layer (170 and bottommost 232, Fig. 35A) and in contact with the first (160 within stack from second 142 to uppermost 142, 131, Fig. 35A) and second (160 within the stack comprising second from the bottom 232 to uppermost 242, Fig. 35A) channel structures ([0242]), wherein a size of the third channel structure (160 within 170 and bottommost 232, Fig. 35A) in a first direction is larger than a size of the first channel structure in the first direction, and the first direction is perpendicular to a stacking direction of the first stacked layer; A first filling structure (162 within stack from second 142 to uppermost 142, 131, Fig. 35A) in contact with an inner surface of the first channel structure ([0240]); and A second filling structure (162 within the stack comprising second from the bottom 232 to uppermost 242, Fig. 35A, Fig. 35A) in contact with the first filing structure and an inner surface of the second channel structure ([0240]); A third filling structure (162 within 170 and bottommost 232, Fig. 35A) in contact with an inner surface of the third channel structure, and connected between the first filling structure and the second filling structure, a size (width of 162 within bottommost 232, Fig. 35A) of the third filling structure (162 within 170 and bottommost 232, Fig. 35A) in the first direction is less than the size of the first channel structure (160 within stack from second 142 to uppermost 142, 131, Fig. 35A); Wherein a bottom portion (160 within bottommost 142 and 10, Fig. 35A) of the channel structure comprises: A bottom surface lower than a bottom surface of the first stacked layer, and A top surface higher than the bottom surface of the first stacked layer and lower than a top surface of the first stacked layer ([0242]; Fig. 35A). Regarding claim 2, Liu discloses the size of the third channel structure (160 within 170, Fig. 35A) in the first direction is larger than a size of the second channel structure (160 within the stack comprising 242, all 232 above bottommost 232, Fig. 35A) in the first direction. Regarding claim 3, Liu discloses the first filling structure (162 within stack from second 142 to uppermost 142, 131, Fig. 35A) and the second filling structure (162 within the stack comprising second 232 to uppermost 242, Fig. 35A) are continuous ([0240]). Regarding claim 4, Liu discloses the second channel structure (160 within the stack comprising 242, all 232 above bottommost 232, Fig. 35A), the third channel structure (160 within 170 and bottommost 232, Fig. 35A), and the first channel structure (160 within stack from second 142 to uppermost 142, 131, Fig. 35A) are continuous. Claim 5 is a product-by-process claim so method limitations (“…formed in a same process”) are examined with respect to the structure implied by the method steps positively recited. Regarding claim 5, Liu discloses the second channel structure (160 within the stack comprising 232, 242, Fig. 35A), the third channel structure (160 within the stack comprising 242, all 232 above bottommost 232, Fig. 35A) and the first channel structure (160 within stack from second 142 to uppermost 142, 131, Fig. 35A) are formed ([0242]). Regarding claim 11, Liu discloses a semiconductor device, comprising: A first stacked layer (second 142 from the bottom to uppermost 142, 131, Fig. 35A) ([0198]); An insulating layer (170 and bottommost 232, Fig. 35A) disposed over the first stacked layer ([0205]); A second stacked layer (second 232 from the bottom to uppermost 242, Fig. 35A) disposed over the insulating layer ([0222]); and A channel structure (160, 163, Fig. 35A) extending through the second stacked layer, the insulating layer and the first stacked layer ([0242]); and A filling structure (162, Fig. 35A) extending through the insulating layer ([0240]), wherein a portion of the channel structure (160, 163, Fig. 35A) is in contact with a topmost surface of the filling structure (162, Fig. 35A), Wherein a size of a third portion of the channel structure (160 within 170 and bottommost 232, Fig. 35A) located in the insulating layer (170, bottommost 232, Fig. 35A) in a first direction is larger than a size of a first portion of the channel structure located in the first stacked layer (second 142 from the bottom to uppermost 142, 131, Fig. 35A) in the first direction; And, a size (width of 162 within bottommost 232, Fig. 35A) And the first direction is perpendicular to a stacking direction of the first stacked layer; Wherein a bottom portion (160 within bottommost 142 and 10, Fig. 35A) of the channel structure comprises: a bottom surface lower than a bottom surface of the first stacked layer, and a top surface higher than the bottom surface of the first stacked layer and lower than a top surface of the first stacked layer ([0242]; Fig. 35A). Regarding claim 12, Liu discloses the channel structure (160, 163, Fig. 35A) is continuous ([0242]). Regarding claim 15, Liu discloses the size (width of 160 within 170, Fig. 35A) of the third portion of the channel structure (160 within 170 and bottommost 232, Fig. 35A) located in the insulating layer (170 and bottommost 232, Fig. 35B) in the first direction is larger than a size of a second portion of the channel structure (160, 163, Fig. 35A) located in the second stacked layer (second 232 from the bottom to uppermost 242, Fig. 35A) in the first direction. Regarding claim 16, Liu discloses a semiconductor device, comprising: A first stacked layer (second 142 from the bottom to uppermost 142, 131, Fig. 35A) ([0198]); An insulating layer (170 and bottommost 232, Fig. 35A) disposed over the first stacked layer ([0205]); A second stacked layer (second from the bottommost 232 to uppermost 242, Fig. 35A) disposed over the insulating layer ([0222]); A channel structure (160, Fig. 35A) extending through the second stacked layer, the insulating layer and the first stacked layer, wherein a size of a third portion of the channel structure (160 within 170 and bottommost 232, Fig. 35A) located in the insulating layer (170 and bottommost 232, Fig. 35A) in a first direction is larger than a size of a first portion of the channel structure located in the first stacked layer in the first direction, the first direction is perpendicular to a stacking direction of the first stacked layer, the channel structure is continuous ([0242]); and A first filling structure (162 within stack from second 142 to uppermost 142, 131, Fig. 35A) in contact with an inner surface of the first portion of the channel structure ([0240]); and A second filling structure (162 within the stack second 232 to uppermost 242, Fig. 35A) in contact with an inner surface of a second portion of the channel structure located in the second stacked layer ([0240]); And a third filling structure (162 within 170 and bottommost 232, Fig. 35A) in contact with an inner surface of the third portion of the channel structure, and connected between the first filling structure and the second filling structure, a size (width of 162 within bottommost 232, Fig. 35A) of the third filling structure (162 within 170 and bottommost 232, Fig. 35A) in the first direction is less than the size of the first portion of the channel structure; Wherein a bottom portion (160 within bottommost 142 and 10, Fig. 35A) of the channel structure comprises: a bottom surface lower than a bottom surface of the first stacked layer, and a top surface higher than the bottom surface of the first stacked layer and lower than a top surface of the first stacked layer ([0242]; Fig. 35A). Regarding claim 17, Liu discloses the size of the portion of the channel structure (160 within 170 and bottommost 232, Fig. 35A) within the insulating layer in the first direction is larger than a size of the channel structure located within the second stacked layer (160 within second from the bottommost 232 to uppermost 242, Fig. 35A) in the first direction. Regarding claim 19, Liu discloses the first filling structure (162 within stack from second 142 to uppermost 142, 131, Fig. 35A) and the second filling structure (162 within the stack comprising bottommost 232 to uppermost 242, Fig. 35A) are continuous ([0240]). Claim(s) 1 and 21 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Costa et al. (U.S. 2018/0182771 A1; “Costa”). Regarding claim 1, Costa discloses a semiconductor device, comprising: A first stacked layer (132, 142, Fig. 11F) ([0126]); An insulating layer (176, Fig. 11F) disposed over the first stacked layer ([0166]); A second stacked layer (232, 242, Fig. 11F) disposed over the insulating layer ([0178]); A channel structure extending through the second stacked layer (232, 242, Fig. 11F), the insulating layer (176, Fig. 11F) and the first stacked layer (132, 142, Fig. 11F), wherein the channel structure comprises: A first channel structure (61, 156, Fig. 11F) extending through the first stacked layer (132, 142, Fig. 11F) ([0156]); A second channel structure (62, 256, Fig. 11F) extending through the second stacked layer (232, 242, Fig. 11F) ([0207]); and A third channel structure (174, 178, Fig. 11F) disposed in the insulating layer (176, Fig. 11F) and in contact with the first (61, 156, Fig. 11F) and second (62, 256, Fig. 11F) channel structures, wherein a size of the third channel structure (174, 178, Fig. 11F) in a first direction is larger than a size of the first channel structure (61, 156, Fig. 11F) in the first direction, and the first direction is perpendicular to a stacking direction of the first stacked layer ([0163], [0174]); A first filling structure (162, Fig. 11F) in contact with an inner surface of the first channel structure (61, 156, Fig. 11F) ([0158]); and A second filling structure (262, Fig. 11F) in contact with an inner surface of the second channel structure (62, 256, Fig. 11F) ([0209]); And a third filling structure (173, 179, Fig. 11F) in contact with an inner surface of the third channel structure (174, 178, Fig. 11F), and connected between the first filling structure (162, Fig. 11F) and the second filling structure (262, Fig. 11F), a size (width of 173, Fig. 11F) of the third filling structure (173, 179, Fig. 11F) in the first direction is less than the size of the first channel structure (61, 156, Fig. 11F); Wherein a bottom portion (11, Fig. 11F) of the channel structure comprises: A bottom surface lower than a bottom surface of the first stacked layer, and A top surface higher than the bottom surface of the first stacked layer and lower than a top surface of the first stacked layer ([0143]). Regarding claim 21, Costa discloses a first portion of a functional layer (162, Fig. 11F) in the first channel structure (61, 156, Fig. 11F) is discontinued with a second portion of the functional layer (262, Fig. 11F) in the second channel structure (62, 256, Fig. 11F) at the third channel structure (174, 178, Fig. 11F). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7, 13, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S. 2016/0204117 A1; “Liu”) as applied to claims 1, 11, and 16 above. Regarding claims 7, 13, and 18, Liu discloses an insulating layer (170 and bottommost 232, Fig. 35A) ([0205], [0223]) within an implicit thickness but does not disclose the thickness must be between 80 nm and 100 nm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select an insulating layer thickness between 80 nm and 100 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Claim(s) 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S. 2016/0204117 A1; “Liu”) as applied to claim 1 above, and further in view of Costa et al. (U.S. 2018/0182771 A1; “Costa”). Regarding claim 6, Liu discloses a third channel structure (160 within 170 and bottommost 232, Fig. 35A) ([0265]) but does not disclose the following: a) The third channel structure comprises polysilicon; b) The thickness of the third channel structure is in a range between 30 nm and 70 nm. Regarding (a), Costa discloses a channel structure comprising polysilicon ([0163], [0174]). Because both Liu and Costa teach methods of forming channel structures, it would have been obvious to one skilled in the art at the time the invention was effectively filed to substitute one method for the other to achieve the predictable result of the third channel structure comprising polysilicon. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Regarding (b), Liu discloses the third channel structure (160 within 170 and bottommost 232, Fig. 35A) has an implicit thickness but does not disclose the thickness must be between 30 nm and 70 nm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select a third channel thickness between 30 nm and 70 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 8, Liu discloses the first stacked layer (second 142 from the bottom to uppermost 142, 131, Fig. 35A) comprises a conductive layer (second 142 from the bottom to uppermost 142, Fig. 35A) and a dielectric layer (131, Fig. 35A) alternatingly stacked ([0198], [0202]) but does not disclose the conductive layer comprises a metal material. However, Costa discloses a first stacked layer (132, 142, Fig. 11F) comprises a conductive layer (142, Fig. 11F) and a dielectric layer (132, Fig. 11F) alternatingly stacked ([0126]) wherein the conductive layer comprises a metal material ([0126]). Because both Liu and Costa teach methods of forming stacked layers comprising alternately stacked sub-layers including sacrificial materials, it would have been obvious to one skilled in the art at the time the invention was effectively filed to substitute one method for the other to achieve the predictable result of forming the conductive layer of the first stacked layer comprising a metal material. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S. 2016/0204117 A1; “Liu”) as modified by Costa et al. (U.S. 2018/0182771 A1; “Costa”) as applied to claim 8 above, and further in view of Fukuzumi et al. (U.S. 2016/0079267; “Fukuzumi”). Regarding claim 9, Liu and Costa discloses the first stacked layer (Costa: 132, 142, Fig. 11F) comprises a conductive layer (Costa: 142, Fig. 11F) and the conductive layer comprises a metal material (Costa: [0126]). Yet, Liu and Costa do not disclose the conductive layer comprises tungsten. However, Fukuzumi discloses a stacked layer comprising tungsten ([0083]). Because both the combination of Liu and Costa and Fukuzumi teach methods of forming stacked layers including sacrificial layers comprising conductive materials, it would have been obvious to one skilled in the art at the time the invention was effectively filed to substitute one method for the other to achieve the predictable result of the conductive layer of the first stacked layer comprising tungsten. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S. 2016/0204117 A1; “Liu”) as applied to claim 11 above, and further in view of Costa et al. (U.S. 2018/0182771 A1; “Costa”). Regarding claim 14, Liu discloses the first stacked layer (second 142 from the bottom to uppermost 142, 131, Fig. 35A) comprises a conductive layer (second 142 from the bottom to uppermost 142, Fig. 35A) and a dielectric layer (131, Fig. 35A) alternatingly stacked ([0198], [0202]) but does not disclose the conductive layer comprises a metal material. However, Costa discloses a first stacked layer (132, 142, Fig. 11F) comprises a conductive layer (142, Fig. 11F) and a dielectric layer (132, Fig. 11F) alternatingly stacked ([0126]) wherein the conductive layer comprises a metal material ([0126]). Because both Liu and Costa teach methods of forming stacked layers comprising alternately stacked sub-layers including sacrificial materials, it would have been obvious to one skilled in the art at the time the invention was effectively filed to substitute one method for the other to achieve the predictable result of forming the conductive layer of the first stacked layer comprising a metal material. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S. 2016/0204117 A1; “Liu”) as applied to claim 16 above, and further in view of Costa et al. (U.S. 2018/0182771 A1; “Costa”). Regarding claim 20, Liu discloses the first stacked layer (second 142 from the bottom to uppermost 142, 131, Fig. 35A) comprises a conductive layer (second 142 from the bottom to uppermost 142, Fig. 35A) and a dielectric layer (131, Fig. 35A) alternatingly stacked ([0198], [0202]) but does not disclose the conductive layer comprises a metal material. However, Costa discloses a first stacked layer (132, 142, Fig. 11F) comprises a conductive layer (142, Fig. 11F) and a dielectric layer (132, Fig. 11F) alternatingly stacked ([0126]) wherein the conductive layer comprises a metal material ([0126]). Because both Liu and Costa teach methods of forming stacked layers comprising alternately stacked sub-layers including sacrificial materials, it would have been obvious to one skilled in the art at the time the invention was effectively filed to substitute one method for the other to achieve the predictable result of forming the conductive layer of the first stacked layer comprising a metal material. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Response to Arguments Applicant’s arguments with respect to claims 1-9 and 11-21 have been considered but are moot in view of the new ground(s) of rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to REEMA PATEL whose telephone number is (571)270-1436. The examiner can normally be reached M-F, 8am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /REEMA PATEL/Primary Examiner, Art Unit 2812 10/7/2025
Read full office action

Prosecution Timeline

Show 3 earlier events
Feb 11, 2025
Final Rejection mailed — §102, §103
Feb 24, 2025
Response after Non-Final Action
May 11, 2025
Request for Continued Examination
May 12, 2025
Response after Non-Final Action
May 23, 2025
Non-Final Rejection mailed — §102, §103
Jul 24, 2025
Response Filed
Oct 09, 2025
Final Rejection mailed — §102, §103
Nov 25, 2025
Response after Non-Final Action

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Prosecution Projections

4-5
Expected OA Rounds
89%
Grant Probability
95%
With Interview (+6.4%)
2y 0m (~0m remaining)
Median Time to Grant
High
PTA Risk
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