The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
Applicant’s amendments and remarks filed 6/22/26 are acknowledged. Claim 1 has been amended. Claims 1 – 20 are pending.
Response to Amendments / Arguments
Amended claim 1 includes new limitations drawn to two dielectric layers in which photonic components and waveguide are disposed respectively. Amended claim 1 obviates the previously raised rejection under 35 USC 102 and necessitates new rejections under 35 USC 103 using a reference by Li et al (US 2021/0116637 A1) that has been yielded by an updated prior art search and, in combination with other prior art, meets all of the limitations recited by amended claim 1, as detailed below.
Applicant's arguments regarding the previously-raised rejections of claims 9 – 20 have been fully considered but they are not persuasive.
Claims 9 and 17:
(a) With respect to claim 17, Applicant asserts that “The Office Action has not yet illustrated how the cited reference teaches or suggests all of the recited features of claim 17. For example, the Office Action has not yet illustrated how the cited reference teaches or suggests the feature "forming a plurality of photonic components over the plurality of first waveguides” (Emphasis added)” (1st complete para. on p. 15 of the Remarks)
The Examiner respectfully disagrees and notes the following:
(i) There is no requirement that the Office Action must include an illustration(s).
(ii) While Figs. 3 and 9 of Yu schematically show that the photonic devices 106A,106B have the same depth and are disposed on the same level as the optical waveguide 104, Yu details that “The photonic components 106A-B may be integrated with the waveguides 104, and may be formed with the silicon waveguides 104” (para. 0030) and that “the photodetectors 106A may be formed by, for example, partially etching regions of the waveguides 104 and growing an epitaxial material on the remaining silicon of the etched regions” (para. 0031, emphasis added). Thus, Yu expressly teaches at least one embodiment wherein the silicon waveguides 104 are not etched through their entire thickness and the photonic devices 106A are formed/disposed over a (remaining) portion of the silicon waveguides 104 to thereby be optically coupled to the silicon waveguides 104.
(b) With respect to claim 9, Applicant alleges that “the Office Action also recites that the assertedly taught waveguide is "within the active photonic interposer in Fig. 10 of Schultz." (Office Action, p. 9) Applicant submits that the Office Action has identified this asserted waveguide is within Schultz's active photonic interposer and has not identified a waveguide within Schultz's asserted photonic structure (PIC 80) as required by claim 9. Thus, the Office Action has failed to illustrate that the references teach or suggest a photonic structure comprising a waveguide that optically couples a first device region of the photonic structure to a second device region of the photonic structure, as recited in claim 9. Applicant also notes that Schultz does not recite the word "waveguide" and does not recite that any of its structures comprises a waveguide” (para. bridging pp. 16 – 17).
The Examiner respectfully disagrees and notes the following:
(i) Notwithstanding Applicant’s mention in passing of Yu, Applicant attempts to critique the Schultz reference individually by pointing out its alleged deficiency instead of addressing the entire Schultz – Yu combination. Hence, Applicant’s arguments are not responsive to the actual rejections. In this regard, Applicant is reminded that it is the Schultz – Yu combination, not the individual references, that is to teach expressly or render obvious all of the limitations recited by the claim. Applicant should address deficiencies (e.g., missing elements), if any, of the entire combination, not the individual references (MPEP 2145, Section IV).
(ii) The Office Action of 3/23/26 clearly explained how the teachings of Yu (about the use of optical waveguides 104 in a photonic integrated package circuit 100) are applied to show internal particulars of the schematically shown boxes of the photonic integrated circuit 80 and the active photonic packages/interposers 82 in Figs. 8 and 11. Hence, Applicant’s assertion that “Schultz does not recite the word "waveguide" and does not recite that any of its structures comprises a waveguide” is without merit and indirectly disregards the very essence of the Schultz – Yu combination. There would not have been a need for the Yu reference, if Schultz expressly stated or explicitly illustrated optical waveguides within the photonic integrated circuit 80 and the active photonic packages/interposers 82, even though the presence of constituent optical waveguides is common knowledge in the art. Applicant failed to address the fact that the very term “photonic integrated circuit” implied the presence of a circuit formed by optical traces/conduits, e.g., waveguides. Just as an electronic integrated circuit is not possible without electrical traces, a photonic integrated circuit is not possible without optical waveguide interconnections.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 17 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu et al (US 2021/0091056 A1).
Regarding claim 17, Yu teaches (Figs. 7, 24, and 25) a method of making an optoelectronic package 300 (as identified in Fig. 24), the method comprising the steps of:
forming a photonic interconnect structure 100 (comprising 110 and 120), comprising:
forming a plurality of first waveguides 104 (detailed in Fig. 7);
forming a plurality of photonic components 106,107 over the plurality of first waveguides 104 (“The photonic components 106A-B may be integrated with the waveguides 104, and may be formed with the silicon waveguides 104” at para. 0030; “the photodetectors 106A may be formed by, for example, partially etching regions of the waveguides 104 and growing an epitaxial material on the remaining silicon of the etched regions” at para. 0031, emphasis added; also para. 0033);
forming an interconnect structure 120 over the plurality of photonic components 106,107 (as shown in Fig. 7); and
bonding an electronic die 122 to the interconnect structure 120 (as shown in Fig. 24);
bonding the photonic interconnect structure 100 to an interposer 250 (shown in Fig. 24); and
bonding a plurality of semiconductor dies 324,326 (Fig. 24) to the interposer 250, wherein the plurality of semiconductor dies 324,326 are electrically connected to the photonic interconnect structure 110,120 (“The interconnect device 50 provides electrical connection between devices attached to the interposer structure 250 in the photonic system 300, such as between a photonic package 100 and a processing die 324 and/or a memory die 326 (see FIG. 24)” at para. 0017, emphasis added).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 8 are rejected under 35 U.S.C. 103 as being unpatentable over Schultz et al (US 2025/0300146 A1) in view of Li et al (US 2021/0116637 A1).
Regarding claim 1, Schultz discloses (Figs. 8 – 11; para. 0129 – 0133) a package comprising (with reference to Fig. 10):
an interposer 82 (formed as a single element or a plurality of separate elements; para. 0129);
a photonic interconnect structure (comprising a photonic integrated circuit (PIC) 80) connected (via microbumps 18b; para. 0132) to the interposer 82; and
and a plurality of dies 81 (as shown in Fig. 8) electrically connected (via the microbumps 18b; para. 0132) to the interposer 82, wherein the dies of the plurality of dies 81 are electrically coupled to the photonic interconnect structure 80 through the interposer 82 (“photonic integrated circuits (PICs) 80 and electronic Integrated Circuits (EICs) 81 are connected through single or multiple active and/or passive photonic interposer 82” at para. 0129).
Schultz shows the photonic interconnect structure 80 only schematically (Figs. 8 and 10) and does not detail its internal structure (structural particulars). However, Li discloses (Figs. 1 and 3; para. 0021 – 0028) a photonic interconnect structure 100 comprises:
a plurality of photonic components 112,113,114,115 in a first (upper) dielectric layer (a SiO2 layer formed over and covering a patterned (silicon) layer 303 in which the photonic components 114,115 are patterned; Figs. 3h and 3i; “photonic circuitry made of various optical building blocks such as grating structure 111, different optical waveguide 112, 113, modulator 114, epitaxially grown Ge photodiode 115. For active device 114, and 115, there are also various electrical connections 116 to them” at para. 0021, para. 0027 and 0028);
a plurality of waveguides 121,122,123,124 (“different waveguide or devices 121, 122, 123, 124” at para. 0021) is a second (lower) dielectric layer (a SiO2 layer(s) formed a preceding step(s) and comprising 304 and 321, as shown in Figs. 3a – 3c; para. 0025), wherein the plurality of waveguides 121,122,123,124 is optically coupled to the plurality of photonic components 112,113,114,115 (“It is worthwhile to mention that the optical coupling between the build block 112 and feature 122 allows light passes between the photonic path in layer 110 and the optical circuitry in layer 120 through evanescence coupling with optical mode size matching” at para. 0033; also para. 0022), and
an electronic die 206 that is electrically coupled to the plurality of photonic components 112,113,114,115 (as shown in Fig. 2; “It is schematically shown here that chips 204 and 206 connects with the modulator and photodetector (referred FIG. 1) to illustrate the fact that the data communication between the chips 204 and 206 is carried out by the optical waveguide built inside the active photonic interposer” at para. 0024).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the photonic interconnect structure in Schultz can have structural particulars as disclosed by Li, so that its photonic devices and optical waveguides form a multifunctional PIC (performing light modulation and detection; para. 0021 of Li) and the photonic devices receive/transmit electrical signals to the comprised electronic die 206 (para. 0024 of Li).
In light of the foregoing analysis, the Schultz – Li combination teaches expressly or renders obvious all of the recited limitations.
Regarding claim 2, the Schultz – Li combination considers (Fig. 10 of Schultz) that the photonic interconnect structure 80 (corresponding to 80 in Fig. 10 of Schultz and having structural particulars of 100 in Yu) can be connected to the interposer 82 through solder bumps 18b (para. 0132 of Schultz).
Regarding claim 3, the Schultz – Li combination renders obvious that the photonic interconnect structure 80 (corresponding to 80 in Fig. 10 of Schultz and having structural particulars of 100 in Yu) can be connected to the interposer 82 through metal-to-metal bonds (vias and solder bumps 18b; para. 0132 of Schultz; 202 in Fig. 2 of Li) and dielectric-to-dielectric bonds (oxide-to-oxide bonding (para. 0132 of Schultz; para. 0021 of Li).
Regarding claim 4, the Schultz – Li combination considers that the plurality of waveguides can be silicon nitride waveguides (para. 0008, 0010, 0012, and 0021 of Li).
Furthermore, the Examiner took official notice in the Office Action of 3/23/26 that waveguides with silicon nitride cores were well known in the art and commonly used as passive waveguides due to their low optical loss. Since Applicant has not traversed the official notice, the fact of common knowledge has become applicant admitted prior art. It is also noted that it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. See In re Leshin, 125 USPQ 416.
Regarding claim 5, the Schultz – Li combination considers that the interposer 82 (Figs. 8 and 01 of Schultz) comprises a plurality of conductive redistribution layers (RDLs) in a plurality of polymer dielectric layers (para. 0094 and 0132 of Schultz).
Regarding claim 6, the Schultz – Li combination considers that the package further comprises a fiber array unit (86 in Schultz; para. 0021 of Li) attached (e.g., via an edge coupler 203 in Fig. 2 of Li; para. 0024) to the electronic die (the entire assembly is integral), wherein the fiber array unit is optically coupled to the plurality of waveguides (via a grating coupler 111; para. 0021 and 0024).
Regarding claims 7 and 8, the Schultz – Li combination considers that the dies 81 of the plurality of dies are electrically coupled to respectively corresponding separate device regions of the photonic interconnect structure (as shown in Fig. 8 of Schultz which shows multiple dies 81 electrically coupled to respectively corresponding separate device regions of the photonic interconnect structure 80), wherein the device regions of the photonic interconnect structure 80 respectively comprise corresponding regions of the electronic die 206 and corresponding sets of photonic components of the plurality of photonic components (Fig. 2 of Li shows at least 2 separate device regions, each region comprising a photonic interconnect structure and a corresponding electronic die 206).
Claims 9 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Schultz et al (US 2025/0300146 A1) in view of Yu.
Regarding claim 9, Schultz discloses (Figs. 8 – 11; para. 0129 – 0133) a package comprising a photonic interconnect structure 80 (Figs. 8 and 10 of Schultz) connected to an interposer 82.
Schultz shows the photonic interconnect structure 80 only schematically (Figs. 8 and 10) and does not detail its internal structure (structural particulars). However, Yu discloses (Figs. 7, 24, and 25) a package 300 (as identified in Fig. 24) comprising:
an interposer 250;
a photonic interconnect structure 100 connected (by vias 112, as shown in Figs. 7 and 24) to the interposer 82 (“the photonic package 100 acts as an input/output (I/O) interface between optical signals and electrical signals in the photonic system 300 (see FIG. 24)” at para. 0028), wherein the photonic interconnect structure 100 comprises:
a plurality of photonic components 106A,106B,107 (as shown in Fig. 7);
a plurality of waveguides 104 that are optically coupled to the plurality of photonic components 106A,106B,107 (“The photonic components 106A-B may be integrated with the waveguides 104, and may be formed with the silicon waveguides 104” at para. 0030; “In some embodiments, one or more couplers 107 may be integrated with the waveguides 104, and may be formed with the waveguides 104” at para. 0033) and
an electronic die 122 that is electrically coupled to the plurality of photonic components 106A,106B (as shown in Fig. 7; “In this manner, the photonic components 106A-B may convert electrical signals (e.g., from an electronic die 122, see FIG. 8) into optical signals transmitted by the waveguides 104, and/or convert optical signals from the waveguides 104 into electrical signals (e.g., that may be received by an electronic die 122)” at para. 0038); and
a plurality of dies 324,326 (as shown in Fig. 24) electrically connected to the interposer 250, wherein the dies of the plurality of dies 324,326 are electrically coupled to the photonic interconnect structure 100 through the interposer 250 (“FIG. 1 illustrates a cross-sectional view of an interconnect device 50, in accordance with some embodiments. The interconnect device 50 will be incorporated into an interposer structure 250 (see FIG. 22) in subsequent processing to form a photonic system 300 (see FIG. 24). The interconnect device 50 provides electrical connection between devices attached to the interposer structure 250 in the photonic system 300, such as between a photonic package 100 and a processing die 324 and/or a memory die 326 (see FIG. 24)” at para. 0017, emphasis added).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the photonic interconnect structure in Schultz can have structural particulars as disclosed by Yu, so that its photonic devices and optical waveguides form a multifunctional PIC (performing light generation, modulation and detection; para. 0030 of Yu) and the photonic devices receive/transmit electrical signals to the comprised electronic die (122 in Yu
; para. 0038) in their close proximity which facilitates high transmission/operational speeds (para. 0016, 0074, and 0079 of Yu).
The Schultz – Yu combination considers a package comprising:
a photonic structure 80 (Figs. 8 and 10 of Schultz) connected to an interconnect structure 82 (interposer), wherein the photonic structure comprises a first device region, a second device region, and a waveguide (104 in Yu) (Fig. 8 of Schutlz illustrates 8 device regions of the photonic structure 80), wherein the first device region comprises a first photonic component (photonic devices 106,107, as detailed by Yu in Figs. 7 and 24), wherein the second device region (has structural particulars similar/identical to those of the first region) comprises a second photonic component, wherein the first device region is optically coupled to the second device region by the waveguide (e.g., within the active photonic interposer in Fig. 10 of Schultz which comprises photonics; para. 0132);
a first package component (internal electronic die 122, according to Yu and/or die 81 in Figs. 8 and 10 in Schultz) connected to the interconnect structure 82, wherein the first package component 81 is electrically coupled to the first device region (as taught by Yu; Fig. 24); and a second package component (internal electronic die 122, according to Yu) connected to the interconnect structure 82, wherein the second package component is electrically coupled to the second device region (as taught by Yu; Fig. 24).
In light of the foregoing analysis, the Schultz – Yu combination teaches expressly or renders obvious all of the recited limitations.
Regarding claims 10 and 11, the Schultz – Yu combination considers that the first package component comprises a first integrated circuit die (122 in Yu; 81 in Schultz) and a second integrated circuit die bonded to an active interposer (“active photonic interposer” shown in Fig. 10), wherein the first integrated circuit die is electrically coupled to the first device region of the photonic structure and the second integrated circuit die is electrically coupled to a third device region of the photonic structure.
Regarding claim 12, the Schultz – Yu combination considers (e.g., Fig. 8 of Schultz) that the first package component is a first semiconductor die 81 and the second package component is a second semiconductor die 81.
Regarding claim 13, the Schultz – Yu combination considers (e.g., Figs. 8 and 10 of Schultz) that the first photonic component 80 and the second photonic component 80 are formed on a substrate 10 (silicon handle), wherein the first device region and the second device region respectively comprise different portions of the substrate (as evident from Fig. 8), wherein the substrate 10 (silicon handle) is free of passive devices and active devices.
Regarding claim 14, the Schultz – Yu combination considers that the substrate (10 in Fig. 10 which corresponds to substrate 302 in Fig. 224 of Yu) can be a silicon substrate (as in Schultz) or a glass substrate (as in Yu; “The interconnect substrate 302 may be for example, a glass substrate, a ceramic substrate, a dielectric substrate” at para. 0075).
Regarding claim 15, the Schultz – Yu combination considers that the photonic structure comprises an electronic die (corresponding to 122 in Yu; Fig. 24), wherein a first portion of the electronic die within the first device region (one of 80 in Fig. 8 of Schultz) is electrically coupled to the first photonic component and a second portion of the electronic die within the second device region (another one of 80 in Fig. 8 of Schultz) is electrically coupled to the second photonic component.
Regarding claim 16, the Schultz – Yu combination considers (Figs. 8 and 10 of Schultz; Fig. 24 of Yu) that the first package component is electrically coupled to the first photonic component and the second package component is electrically coupled to the second photonic component, as was detailed above for claims 1 and 9.
Regarding claim 17, the teachings of Schultz and Yu combine (see the arguments and motivation for combining, as provided above for claim 1) to teach expressly or render obvious all of the recited step limitations of a corresponding method of making the contemplated package, as detailed above for claim 1. Specifically, the Schultz – Yu combination considers a method comprising:
forming a photonic interconnect structure (100 in Fig. 24 of Yu which corresponds to 80 in Figs. 8 and 10 of Schultz), comprising:
forming a plurality of first waveguides 104 (detailed in Fig. 7 of Yu);
forming a plurality of photonic components 106,107 over the plurality of first waveguides 104 (para. 0030 and 0033 of Yu);
forming an interconnect structure 120 over the plurality of photonic components 106,107 (“The photonic components 106A-B may be integrated with the waveguides 104, and may be formed with the silicon waveguides 104” at para. 0030; “the photodetectors 106A may be formed by, for example, partially etching regions of the waveguides 104 and growing an epitaxial material on the remaining silicon of the etched regions” at para. 0031, emphasis added; also para. 0033); and
bonding an electronic die 122 to the interconnect structure 122 (as shown in Fig. 24);
bonding the photonic interconnect structure 100 to an interposer (250 in Fig. 24 of Yu which corresponds to 82 in Figs. 8 and 10 of Schultz); and
bonding a plurality of semiconductor dies (324,326 in Fig. 24 of Yu which correspond to 81 in Figs. 8 and 10 of Schultz) to the interposer 82, wherein the plurality of semiconductor dies 81 are electrically connected to the photonic interconnect structure 80 (para. 0129 of Schultz).
Regarding claim 18, the Schultz – Yu combination renders obvious a step of forming a plurality of second waveguides within the interconnect structure (e.g., in a second device region, as shown in Fig. 8 of Schultz).
Regarding claim 19, the Schultz – Yu combination renders obvious that bonding the photonic interconnect structure can comprise performing a fusion bonding process (para. 0043 of Yu).
Regarding claim 20, the Schultz – Yu combination considers that the method can further comprise bonding the interposer to a package substrate (10 in Fig. 10 which corresponds to substrate 302 in Fig. 224 of Yu).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2023/0244029 A1
US 2021/0271037 A1
US 2024/0353614 A1
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT TAVLYKAEV whose telephone number is (571)270-5634. The examiner can normally be reached 10:00 am - 6:00 pm, Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERT TAVLYKAEV/Primary Examiner, Art Unit 2896
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