Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1- are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. 20200043801 to Kim et al. (Kim).
Regarding Claim 1, Kim teaches in Fig. 1 at least, high-voltage semiconductor device comprising:
a substrate 10;
a gate field plate 60 disposed at a substrate surface of the substrate;
a gate region 70 disposed on the substrate, wherein the gate region is partly disposed on the gate field plate; and
a drift region disposed in the substrate, wherein the drift region comprises:
a first impurity region 51 disposed at the substrate surface; and
a second impurity 20 region covering at least one side wall of the first impurity region.
Regarding Claim 2, Kim teaches the high-voltage semiconductor device of claim 1, wherein the drift region has group 15 element impurity ion (N type, must be group 15).
Regarding Claim 4, Kim teaches the high-voltage semiconductor device of claim 1, wherein the second impurity region covers a lower portion of the first impurity region and the at least one side wall of the first impurity region (see Fig. 1).
Regarding Claim 5, Kim teaches the high-voltage semiconductor device of claim 1, wherein the first impurity region is formed by using a hard mask that is used for forming the gate field plate (product by process limitations do not bear weight, see MPEP 2113).
Regarding Claim 6, Kim teaches the high-voltage semiconductor device of claim 1, further comprising:
a body region 30 disposed in the substrate;
a source region 45 disposed at the substrate surface, in the body region; and
a drain region 25 disposed apart from the source region, the drain region being disposed at the substrate surface and in the substrate.
Regarding Claim 7, Kim teaches the high-voltage semiconductor device of claim 6, further comprising:
a drain extension region 23 covering the drain region, the drain extension region being disposed in the substrate, wherein the drain extension region has an impurity low concentration doped region in comparison to the drain region (N+ vs. N).
Regarding Claim 8, Kim teaches a high-voltage semiconductor device comprising:
a substrate 10;
a gate field plate 60 disposed at a substrate surface of the substrate;
a gate region 70 disposed on the substrate, wherein the gate region is partly disposed on the gate field plate;
a drift region 20 of a second conductivity type N disposed in the substrate;
a body region 30 of a first conductivity type P disposed in the substrate;
a source 45 region of the second conductivity type disposed in the body region; and
a drain region 25 of the second conductivity type disposed in the drift region, wherein the drift region comprises:
a first impurity region 51 disposed at the substrate surface; and
a second impurity region 20 disposed below the first impurity region, wherein the first impurity region comprises:
a protruding region protruding towards the source region from a part of the first impurity region facing the source region (see Fig. 1).
Regarding Claim 9, Kim teaches the high-voltage semiconductor device of claim 8, wherein the second impurity region covers the protruding region (see Fig. 1).
Regarding Claim 11, Kim teaches the high-voltage semiconductor device of claim 8, wherein the drift region has an impurity low concentration doped region in comparison to the drain region.
Regarding Claim 12, Kim teaches the high-voltage semiconductor device of claim 8, wherein the drift region is formed immediately before a formation process of the gate field plate (N+ vs. N).
Allowable Subject Matter
Claims 3 and 10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The cited prior art does not teach that the second impurity region has group 15 element impurity ion having atomic weight smaller than atomic weight of the group 15 element impurity ion of the first impurity region or that the second impurity region comprises: a first layer disposed below the first impurity region in the substrate; and a second layer disposed below the first layer in the substrate in context with the superseding claims.
Conclusion
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/EVREN SEVEN/Primary Examiner, Art Unit 2812
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