Prosecution Insights
Last updated: October 25, 2026
Application No. 18/431,815

METHOD FOR MANUFACTURING TRANSISTOR DEVICE, AND TRANSISTOR DEVICE

Final Rejection §102
Filed
Feb 02, 2024
Priority
Feb 03, 2023 — CN 202310118993.1
Examiner
JUNG, MICHAEL YOO LIM
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BITMAIN TECHNOLOGIES INC.
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
1072 granted / 1295 resolved
+14.8% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
22 currently pending
Career history
1326
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
30.7%
-9.3% vs TC avg
§102
33.4%
-6.6% vs TC avg
§112
28.8%
-11.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1295 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION In response to an Office action mailed on 04/03/2026 (“04-03-26 OA”), the Applicant substantively amended claims 1 and 2 and canceled claimed 12 on 07/02/2026 ("07-02-26 Response”). The Applicant amended the title and the Specification in the 07-02-26 Response. Currently, claims 1-11 and 13-15 are pending. Response to Arguments Applicant’s amendments to the title have overcome the objection to the Specification as set forth on page 2 under line item number 1 of the 04-03-26 OA. Applicant’s amendments to the independent claim 1 and the cancelation of claim 12 have overcome the 35 U.S.C. 112(b) rejection of claims 1-15 as set forth on page 3 under line item number 2 of the 04-03-26 OA. Despite the substantive amendments to the independent claim 1, previously-cited Bordelon reads on the amended independent claim 1. On page 10 of the 07-02-26 Response, the Applicant argues that “However, in Bordelon, it is explicitly stated that ‘Disclosed retrograde doped regions are positioned in an appropriate depth range so that they are deep enough to not significantly alter electrical characteristics of devices within the well including the threshold voltages (Vt) of MOS devices in the well, the well-substrate breakdown voltage and well-substrate capacitance,” so Bordelon does not teach the amended feature of “wherein an amount of injection of the doping ions is associated with at least one of the following: a present threshold voltage and a target threshold voltage of a transistor.” The examiner respectfully disagrees. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Currently amended, the claim does not recite the extent of the association or causation of the amount of injection of the doping ions to either a present threshold voltage or a target threshold voltage of a transistor so the Applicant’s argument that the amended feature distinguishes over the method taught by Bordelon based on the extent is not persuasive in light of the fact that Bordelon does not say that there is no effect on the threshold voltage of the MOS devices by injecting B+ ions to form retrograde doped regions, but rather provides a ceiling of the retrograde dope regions “not significantly” altering the threshold voltage. Substantively-amended independent claim 1 and its dependent claims required further consideration and search. New grounds of rejection are provided below. Claim Rejections - 35 USC § 102 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1 and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bordelon (previously-cited Pub. No. US 2014/0042545 A1 to Bordelon, Jr et al.). Fig. 3 of Bordelon has been annotated to support the rejection below: [AltContent: textbox (channel of NMOS 320 )][AltContent: textbox (Retrograde doped region 220 region of PMOS 340 (“RDR 220 of 340”))][AltContent: arrow][AltContent: rect] PNG media_image1.png 295 588 media_image1.png Greyscale Regarding independent claim 1, Bordelon teaches a method for manufacturing a transistor device (see Fig. 3), comprising: injecting, into a channel 210 (para [0022] - “The position of peak doping for each of the boron high energy implant is set by the implant energy (and stopping power of the substrate) such that implanted profile encroaches minimally into the nwell 210 and nwell-substrate depletion region 215.”) of at least one first transistor 340 (PMOS) located in an electrical break (EB) region RDR 220 of 340 (para [0021] - “FIG. 2A illustrates simulations of two example high energy implant conditions which form a retrograde doped region that significantly increase the p-type doping in the substrate below the nwell-substrate depletion region 215. The example of implant conditions are shown as 11B+ dose of 4x1012 cm-2 at 750 keV, and a 11B+ dose of 1x1013 cm-2 at 750 keV.” see Fig. 2A; para [0022] - “The retrograde doped region 220”; para [0024] - “Disclosed retrograde doped regions involve a different design objective and subsequent well design and doping profiles for achieving reduced leakage, being suppression of minority carriers within a diffusion length of the well depletion region to reduce junction leakage.”), doping ions (boron ions) of a different type (n-type dopant of the nwell 210) from the first transistor 340 (PMOS), and injecting, into a channel of at least one second transistor 320 (para [0025] - “an NMOS transistor 320”) located outside the EB region RDR 220 of 340, doping ions (B+) of a same type as the second transistor 340 (Fig. 3 shows the retrograde doped region 220 that also exists under the channel of the NMOS 320.); and forming the transistor device 330 based on the first transistor 340 (PMOS) and the second transistor 320 (NMOS) into which doping ions (B+) have been injected. A limitation of “wherein an amount of injection of the doping ions is associated with at least one of the following: a present threshold voltage and a target threshold voltage of a transistor” is directed to an intended use or an intended result, so it may not distinguish the claimed method over the method taught by Bordelon. Since Bordelon teaches all of the method steps as recited in claim 1, the method of Bordelon is capable of being used or having the result as intended. Regarding claim 13, Bordelon teaches a concentration of the doping ions (B+) that is 1012 to 1014 (para [0021] - “FIG. 2A illustrates simulations of two example high energy implant conditions which form a retrograde doped region that significantly increase the p-type doping in the substrate below the nwell-substrate depletion region 215. The example of implant conditions are shown as 11B+ dose of 4x1012 cm-2 at 750 keV, and a 11B+ dose of 1x1013 cm-2 at 750 keV.” see Fig. 2A). The term “or” of the “and/or” has been invoked so a limitation of “energy of the doping ions 1 keV to 10 keV” has been interpreted as being optional. Regarding independent claim 14, Bordelon teaches a transistor device 300 (see Fig. 3), which is manufactured through the method for manufacturing a transistor device according to claim 1. Regarding claim 15, Bordelon teaches the transistor device 300 comprises: an inverter 330 (see Fig. 3). Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: Claim 2 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 2. Claims 3-11 are allowable for depending on the allowable claim 2. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408)918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano, can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL JUNG/Primary Examiner, Art Unit 2817 02 October 2026
Read full office action

Prosecution Timeline

Feb 02, 2024
Application Filed
Apr 03, 2026
Non-Final Rejection mailed — §102
Jul 02, 2026
Response Filed
Oct 06, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
93%
With Interview (+10.5%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1295 resolved cases by this examiner. Grant probability derived from career allowance rate.

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