DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1,10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is not clear what applicant is refereeing to by the limitation “the IMD metal layer”.
Claims 9,19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. According to applicants application and the claims the DC_DC convertor is merely a transistor; however, DC to DC transistor convertor requires a transistor and capacitor and inductor.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2,5,7,10,12,15,17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chou et al (US Pub No. 20250046700).
With respect to claim 1, Chou et al discloses an integrated circuit comprising (Fig.12): a die (120’), comprising an active device layer (126 particularly 126C and 1124) and interconnect layers coupled to the active device layer (56 to 130); and an active power distribution network (PDN) layer (20’), including a power switch (32) and an intermetal dielectric (IMD) layer (28,48), in which the IMD metal layer (for example 30,44) is coupled between the power switch and the die (96).
With respect to claim 2, Chou et al discloses in which the active PDN layer is on a backside of the die (Fig.12).
With respect to claim 5, Chou et al discloses further comprising a via interconnect (127), extending through the active device layer (Fig.5), and coupling a zero metal (M0) layer (lower 144) of the interconnect layers to an M1 metal layer of the IMD layer (44) of the active PDN layer on a backside of the die (Fig.5).
With respect to claim 7, Chou et al discloses further comprising back-end-of-line (BEOL) metal layers of the interconnect layers (130,144,Fig.5) coupled to an M1 metal layer (44) of the IMD layer of the active PDN layer on a frontside of the die (Fig.5).
With respect to claim 10, Chou et al discloses an integrated circuit comprising (Fig.12): forming a die (120’), comprising an active device layer (126 particularly 126C and 1124) and interconnect layers coupled to the active device layer (56 to 130); and forming an active power distribution network (PDN) layer (20’), including a power switch (32) and an intermetal dielectric (IMD) layer (28,48), in which the IMD metal layer (for example 30,44) is coupled between the power switch and the die (96).
With respect to claim 12, Chou et al discloses in which the active PDN layer is on a backside of the die (Fig.12).
With respect to claim 15, Chou et al discloses further comprising a via interconnect (127), extending through the active device layer (Fig.5), and coupling a zero metal (M0) layer (lower 144) of the interconnect layers to an M1 metal layer of the IMD layer (44) of the active PDN layer on a backside of the die (Fig.5).
With respect to claim 17, Chou et al discloses further comprising back-end-of-line (BEOL) metal layers of the interconnect layers (130,144,Fig.5) coupled to an M1 metal layer (44) of the IMD layer of the active PDN layer on a frontside of the die (Fig.5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4,10,13-14,18,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Pub No. 20250046700).
With respect to claim 3, Chou et al does not explicitly disclose in which the active PDN layer is on a frontside of the die. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Chou et al such that the active PDN layer is on a frontside of the die, by just merely flipping the IC as is shown in Fig.13 as a design choice.
With respect to claim 4, Chou et al on Fig.12 does not explicitly disclose further comprising a via interconnect, extending through the active device layer, and coupling a first metal (M1) layer of the interconnect layers to an M1 metal layer of the IMD layer of the active PDN layer on a backside of the die. On the other hand, Chou et al discloses a via interconnect (127,Fig.5), extending through the active device layer (124), and coupling a first metal (M1) layer of the interconnect layers (upper 144) to an M1 metal layer of the IMD layer of the active PDN layer (44 near 56) on a backside of the die (20’). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Chou et al in Fig.12 according to the teachings of the Figure 5 of the same reference such that the via interconnect, extending through the active device layer and couple M1 metal of the active layer to the M1 layer of the PDN layer, in order to couple the entire device to the outside solder bumps.
With respect to claim 8, Chou et al does not explicitly disclose in which the power switch comprises a direct current (DC) to DC (DC-DC) converter. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Chou et al such that the power switch comprises a direct current (DC) to DC (DC-DC) converter, in order to be able to lower or increase voltage of the device for different applications.
With respect to claim 10, Chou et al does not explicitly disclose in which the IC comprises a system-on-chip. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Chou et al such that the IC comprises a system-on-chip, in order to save space and cut the cost.
With respect to claim 13, Chou et al does not explicitly disclose in which the active PDN layer is on a frontside of the die. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Chou et al such that the active PDN layer is on a frontside of the die, by just merely flipping the IC as is shown in Fig.13 as a design choice.
With respect to claim 14, Chou et al on Fig.12 does not explicitly disclose further comprising a via interconnect, extending through the active device layer, and coupling a first metal (M1) layer of the interconnect layers to an M1 metal layer of the IMD layer of the active PDN layer on a backside of the die. On the other hand, Chou et al discloses a via interconnect (127,Fig.5), extending through the active device layer (124), and coupling a first metal (M1) layer of the interconnect layers (upper 144) to an M1 metal layer of the IMD layer of the active PDN layer (44 near 56) on a backside of the die (20’). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Chou et al in Fig.12 according to the teachings of the Figure 5 of the same reference such that the via interconnect, extending through the active device layer and couple M1 metal of the active layer to the M1 layer of the PDN layer, in order to couple the entire device to the outside solder bumps.
With respect to claim 18, Chou et al does not explicitly disclose in which the power switch comprises a direct current (DC) to DC (DC-DC) converter. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Chou et al such that the power switch comprises a direct current (DC) to DC (DC-DC) converter, in order to be able to lower or increase voltage of the device for different applications.
With respect to claim 20, Chou et al does not explicitly disclose in which the IC comprises a system-on-chip. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Chou et al such that the IC comprises a system-on-chip, in order to save space and cut the cost.
Claim(s) 6,16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Pub No. 20250046700), in view of Chan (US Pub No. 20150137324).
With respect to claim 6, Chou et al does not explicitly disclose further comprising micro-bumps to couple the interconnect layers of the die to a first metal (M1) layer of the IMD layer of the active PDN layer on a frontside of the die. On the other hand, Chan discloses bumps (247a,Fig.2) are used to couple all the interconnect layers (such as 255,254,246) of the die from front to back (Fig.2). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Chou et al according to the teachings of the Chan such that micro-bumps to couple the interconnect layers of the die to a first metal (M1) layer of the IMD layer of the active PDN layer on a frontside of the die, in order to make the connections step by step, thereby making a secure and well connection between the interconnect and the first metal of the active PDN.
With respect to claim 16, Chou et al does not explicitly disclose further comprising micro-bumps to couple the interconnect layers of the die to a first metal (M1) layer of the IMD layer of the active PDN layer on a frontside of the die. On the other hand, Chan discloses bumps (247a,Fig.2) are used to couple all the interconnect layers (such as 255,254,246) of the die from front to back (Fig.2). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Chou et al according to the teachings of the Chan such that micro-bumps to couple the interconnect layers of the die to a first metal (M1) layer of the IMD layer of the active PDN layer on a frontside of the die, in order to make the connections step by step, thereby making a secure and well connection between the interconnect and the first metal of the active PDN.
Claim(s) 9,19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Pub No. 20250046700), in view of Reefman et al (US Pub No. 20090146760)
With respect to claim 9, Chou et al does not explicitly disclose a deep trench capacitor (DTC) coupled to the DC-DC converter; and a magnetic inductor coupled to the DTC. On the other hand, Reefman et al discloses a deep trench capacitor (DTC) (102,Fig.4) coupled to the DC-DC converter (Fig.1); and a magnetic inductor coupled to the DTC (114). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Chou et al according to the teachings of the Reefman et al such that a deep trench capacitor (DTC) coupled to the DC-DC converter; and a magnetic inductor coupled to the DTC, in order to make a high frequency DC-DC converter.
With respect to claim 19, Chou et al does not explicitly disclose forming a deep trench capacitor (DTC) coupled to the DC-DC converter; and forming a magnetic inductor coupled to the DTC. On the other hand, Reefman et al discloses a deep trench capacitor (DTC) (102,Fig.4) coupled to the DC-DC converter (Fig.1); and a magnetic inductor coupled to the DTC (114). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Chou et al according to the teachings of the Reefman et al such that a deep trench capacitor (DTC) coupled to the DC-DC converter; and a magnetic inductor coupled to the DTC, in order to make a high frequency DC-DC converter.
Conclusion
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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