Prosecution Insights
Last updated: August 17, 2026
Application No. 18/432,031

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Non-Final OA §102
Filed
Feb 04, 2024
Examiner
SENGDARA, VONGSAVANH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
673 granted / 935 resolved
+4.0% vs TC avg
Strong +18% interview lift
Without
With
+18.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
61 currently pending
Career history
1012
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
51.6%
+11.6% vs TC avg
§102
27.1%
-12.9% vs TC avg
§112
18.2%
-21.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 935 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of invention II and Species 1, drawn to claims 15-17, 19-20 and 21-35 in the reply filed on 05/14/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 15-17 and 19-35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. 20230307318. PNG media_image1.png 461 796 media_image1.png Greyscale Regarding claim 15, fig. 4A of Lee discloses a method of forming a semiconductor device, comprising: forming a device layer 400 and a first routing structure (layer of 440 and 450) over a first substrate 500, the first routing structure electrically connected to the device layer; bonding the first routing structure to a second substrate 700 through a bonding layer 701, wherein the bonding layer comprises a plurality of microchannels 720; and forming a second routing structure 420 over the device layer 400 to electrically connect to the device layer, wherein the device layer 400 is disposed between the first routing structure and the second routing structure. Regarding claim 21, fig. 4 of Lee discloses a method of forming a semiconductor device, comprising: forming a device layer 400 over a first substrate 500; forming a routing structure (620s and all in including and between 100 and 200 – which is a route to 700) over the device layer, comprising a plurality of dielectric layer 800, 820 and 300) and a plurality of conductive features 230; forming a bonding layer 701 comprising a plurality of microchannels 720 over a second substrate 700; and attaching the routing structure to the second substrate through the bonding layer (see fig. 12F). Regarding claim 27, fig. 4A of lee a method of forming a semiconductor device, comprising: providing a device layer 400 over a first substrate 500, the device layer comprising a device (each of 430 is a device); forming a first routing structure (layer of 440/450) at a first surface (bottom surface) of the device layer over the first substrate; bonding a second substrate 700 and a bonding layer 701 comprising a plurality of microchannels 720 to the first routing structure over the first substrate; forming a second routing structure 420 on the second substrate to be disposed at a second surface (top surface) opposite to the first surface of the device layer; and providing a fluid introduction element 910, to flow a fluid CT into the microchannels of the bonding layer. Regarding claim 16, fig. 12F of Lee discloses wherein the microchannels are formed in the bonding layer before bonding the first routing structure to the second substrate. Regarding claim 17, fig. 12F of Lee discloses wherein a method of forming the microchannels comprises: printing the bonding layer, to form the microchannels; and curing the bonding layer (this is necessary (dissipation structure 700 may be formed of a material having high thermal conductivity. For example, the heat dissipation structure 700 may be formed of a metal material, such as copper (Cu), aluminum (Al), stainless steel (SUS) par [0060] and therefore some type of curing is done it). Regarding claim 19, fig. 12F of Lee discloses wherein the microchannels are formed to penetrate through the bonding layer. Regarding claim 20, figs. 12A-B of Lee discloses (fig. 12A shows that 500 formed and therefore it was removed from another bigger piece to form it) further comprising removing a portion of the first substrate before forming the second routing structure. Regarding claim 22, fig. 12F of Lee discloses wherein a method of forming the microchannels comprises: printing the bonding layer (see 701 has to printed somehow), to form the microchannels 720; and curing the bonding layer (dissipation structure 700 may be formed of a material having high thermal conductivity. For example, the heat dissipation structure 700 may be formed of a metal material, such as copper (Cu), aluminum (Al), stainless steel (SUS) par [0060] and therefore some type of curing is done it. Regarding claim 23, fig. 12F of Lee discloses wherein the bonding layer 701 is directly formed on the second substrate 700, and attaching the routing structure to the second substrate through the bonding layer comprises directly attaching the bonding layer to the routing structure (see fig. 12F). Regarding claim 24, fig. 12F of Lee discloses wherein the microchannels expose portions of the dielectric layer and the conductive features of the routing structure after attaching the routing structure to the second substrate. Regarding claim 25, fig. 12F of Lee discloses wherein the microchannels are formed to penetrate through the bonding layer. Regarding claim 26, fig. 4A of Lee discloses wherein the microchannels are sealed between the routing structure and the second substrate after attaching the routing structure to the second substrate. Regarding claim 28, Lee discloses wherein a method of forming the microchannels comprises: printing the bonding layer (it is printed to look as fig. 12F, to form the microchannels 720; and curing the bonding layer (some form heat at some level is use for forming 700). Regarding claim 29, fig. 12F of Lee discloses wherein printing the bonding layer further comprises forming a fluid inlet 701 and a fluid outlet 703 communicated with the microchannels, and providing the fluid introduction element 910 comprises flow the fluid CT into the fluid inlet. Regarding claim 30, fig. 12F of Lee discloses wherein printing the bonding layer comprises penetrating through the bonding layer. Regarding claim 31, fig. 4A of Lee discloses wherein the fluid interfaces with a first dielectric layer 800 and a plurality of first conductive patterns 610s of the first routing structure. Regarding claim 32, fig. 4A of Lee discloses wherein the microchannels comprise a plurality of first microchannels 720 and a second microchannel 710 connecting the first microchannels. Regarding claim 33, fig. 4A of Lee discloses wherein the first microchannels 720 are parallel to each other, and the second microchannel 710 surrounds the first microchannels. Regarding claim 34, Lee discloses wherein the fluid is a dielectric fluid (there is some dielectric constant associated with). Regarding claim 35, figs. 12A-B necessary suggest that before forming the second routing structure, further comprising thinning down a thickness of the first substrate (the thickness of 500 has to be form remove surface angstrom thickness of some type which is thinning as claimed). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PURVIS A. Sue can be reached on (571 )272-1236.. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Feb 04, 2024
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
90%
With Interview (+18.5%)
3y 3m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 935 resolved cases by this examiner. Grant probability derived from career allowance rate.

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