DETAILED ACTION
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20220352090 A1, hereinafter Chen’090).
Regarding independent claim 19, Chen’090 teaches, “A semiconductor package (fig. 1-14; ¶ [0001] - ¶ [0090]) comprising:
a substrate (10, fig. 2);
an interposer (21) disposed on the substrate (10);
at least one semiconductor chip (22) disposed on the interposer (21); and
a stiffener (31, 32) disposed on the substrate (10), the stiffener (31, 32) including a body portion (31) having a cavity (RS1) and a thermally conductive portion (32) within the cavity (RS1),
wherein the body portion (31) includes a lower body (lower part of element 31) providing the cavity (RS1) and an upper body (upper part of element 31) covering the lower body (vertically) and the thermally conductive portion (horizontally), and
a first thermal conductivity of the body portion (stainless steel, ¶ [0049]) is less than a second thermal conductivity of the thermally conductive portion (copper. ¶ [0049]).
Regarding claim 20, Naga’384 further teaches, “The semiconductor package of claim 19, wherein a first tensile strength of the body portion is greater than a second tensile strength of the thermally conductive portion (¶ [0049])”.
Claims 16-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by NAGARAJAN; Kavitha et al. (US 20230420384 A1, hereinafter Naga’384).
Regarding independent claim 16, Naga’384 teaches, “A semiconductor package (fig. 1-7; ¶ [0001] - ¶ [0091]) comprising:
a substrate (202, fig. 2);
at least one semiconductor chip (204) disposed on the substrate (202); and
a stiffener (220, 242) disposed on the substrate (202), the stiffener including a body portion (220) having a cavity (222), and a porous thermally conductive portion (242/240, ‘mesh composites’, ¶ [0035]) within the cavity (222),
wherein the porous thermally conductive portion (242) includes a porous molded body or a mesh-type plate (¶ [0035]),
a tensile strength of the body portion (220/420, ‘stainless steel’, ¶ [0042]) is greater than a tensile strength of the porous thermally conductive portion (242/240, copper, ¶ [0035]), and a thermal conductivity of the porous thermally conductive portion is greater than a thermal conductivity of the body portion (the applicant and Naga’384 use similar materials for body portion and conductive portion of the stiffener)”.
Regarding claim 17, Naga’384 further teaches, “The semiconductor package of claim 16, wherein the body portion (220) includes a lower body (lower portion), providing the cavity (222), and an upper body (upper portion), bonded to the lower body”.
Regarding claim 18, Naga’384 further teaches, “The semiconductor package of claim 16, wherein the body portion (220/420, ¶ [0042]) includes stainless steel (SUS), and the porous thermally conductive portion (242, ¶ [0035]) includes copper (Cu)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen’090 in view of Chiang et al. (US 20240234340 A1, hereinafter Chiang’340).
Regarding independent claim 1, Chen’090 teaches, “A semiconductor package (fig. 1-14; ¶ [0001] - ¶ [0090]) comprising:
a substrate (10, fig. 2) including a first interconnection (¶ [0028], ¶ [0042]);
an interposer (21) disposed on the substrate (10), the interposer (21) including a second interconnection (210) electrically connected (using element 28) to the first interconnection;
first and second semiconductor chips (22, 22’) disposed on the interposer (21), the first and second semiconductor chips (22, 22’) electrically connected to each other through the second interconnection; and
a stiffener (31, 32) disposed on the substrate (10) to be spaced apart from the interposer (21), the stiffener (31, 32) including a body portion (31) having a cavity (RS1), and a ((porous)) thermally conductive portion (32) within the cavity (RS1),
wherein the body portion (31) includes a first material (stainless steel, ¶ [0049]) having a first coefficient of thermal expansion, and
the ((porous)) thermally conductive portion (32, copper. ¶ [0049]) includes a second material having a second coefficient of thermal expansion, greater than the first coefficient of thermal expansion.
But Chen’090 is silent upon the provision of wherein the thermally conductive portion is porous.
However, Chiang’340 teaches a similar semiconductor package (300, fig. 12) with a stiffener (236) comprising thermally conductive porous materials (240).
Chen’090 and Chiang’340 are analogous art because they both are directed to semiconductor package with a stiffener and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen’090 with the features of Chiang’340 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Chen’090 and Chiang’340 to include perforations in the stiffener according to the teachings of Chiang’340 to reduce the stiffness and/or hardness of the stiffener thereby reducing the risk of the cracking of the electrical elements adjacent to the perforated regions. See Chiang’340, ¶ [0006], ¶ [0035].
Regarding claim 2, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 1, wherein the substrate (10, fig. 2) further includes an insulating layer (ceramic etc., ¶ [0027], Chen’090) in which the first interconnection (connection between balls 11 and balls 28) extends, and the second coefficient of thermal expansion (of copper) is greater than a coefficient of thermal expansion of the substrate (ceramic)”. Note: Chiang’340 also teaches similar.
Regarding claim 3, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 2, wherein the coefficient of thermal expansion of the substrate (ceramic) is in a range of about 5 ppm/°C to about 15 ppm/°C, and the first coefficient of thermal expansion (stainless steel) is in a range of about 5 ppm/°C to about 15 ppm/°C”.
Regarding claim 4, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 2, wherein the second coefficient of thermal expansion (copper) is in a range of about 10 ppm/°C to about 20 ppm/°C”.
Regarding claim 5, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 1, wherein a first thermal conductivity of the first material (stainless steel) is less than a second thermal conductivity of the second material (copper)”.
Regarding claim 6, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 5, wherein the first thermal conductivity is in a range of about 10 W/m-K to about 30 W/m.K, and the second thermal conductivity is in a range of about 350 W/m-K to about 450 W/m.K (stainless steel and copper)”.
Regarding claim 6, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 1, wherein a first tensile strength of the first material (stainless steel) is greater than a second tensile strength of the second material (copper)”.
Regarding claim 8, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 7, wherein the first tensile strength (stainless steel) is in a range of about 370 MPa to about 470 MPa, and the second tensile strength is in a range of about 340 MPa to about 440 Mpa (copper)”.
Regarding claim 9, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 1, wherein the first material includes iron (Fe) (stainless steel) or an alloy of iron (Fe), and the second material includes copper (Cu) or an alloy of copper (Cu)”.
Regarding claim 10, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 1, wherein the body portion includes a lower body (lower portion of element 31, fig. 2, Chen’090), providing a sidewall and a bottom of the cavity, and an upper body (upper portion of element 31), covering (horizontally) the cavity (RS2)”.
Regarding claim 12, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 1, wherein the porous thermally conductive portion (236, Chiang’340) is a porous metal molded body”.
Regarding claim 13, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 1, wherein the porous thermally conductive portion is formed of a plurality of mesh-type metal plates (element 236 of Chiang’340 is made of metal)”.
Regarding claim 14, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 1, wherein the stiffener (31, 32, fig. 2, Chen’090) extends on the substrate (10) to surround a side surface of the interposer (21)”.
Regarding claim 15, Chen’090 modified with Chiang’340 further teaches, “The semiconductor package of claim 1, wherein a volume of the body portion (31, Chen’090) is about 10% or more and about 50% or less of a total volume of the stiffener (31, 32)”.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chen’090 modified with Chiang’340 as applied to claim 10 as above, and further in view of Naga’384.
Regarding claim 11, Chen’090 modified with Chiang’340 teaches all the limitations described in claim 10.
But Chen’090 modified with Chiang’340 is silent upon the provision of wherein an adhesive layer disposed between the lower body and the upper body.
However, Naga’384 teaches a similar semiconductor package (fig. 4) comprising an adhesive layer (438) disposed between the lower body (420) and the upper body (442).
Chen’090 modified with Chiang’340 and Naga’384are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen’090 modified with Chiang’340 with the features of Naga’384because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Chen’090 modified with Chiang’340 and Naga’384 to attach the lower and upper bodies using adhesive according to the teachings of Naga’384 as this process is an alternative process which is well known and commonly used in the art for providing attachment between two separate elements in a semiconductor package.
Election/Restrictions
The restriction requirement is withdrawn and all the claims are examined as above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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