DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/20/26 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 16-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (US 2022/0397607).
For claim 1, Figure 13 of Kang teaches a circuit comprising: a master latch (100) configured to receive a data signal (D) and a first timing signal (bclk) having a first phase and to generate a master latch output signal (M3) based on the data signal (D) and the first timing signal (bclk); wherein the first (MP143 inside 145, see Figure 16) and second (MP125 inside 125, see Figure 14) transistors of the master latch are configured to receive the first timing signal (bclk), and each of first (MP143 inside 145, see Figure 16) and second (MP125 inside 125, see Figure 14) transistors includes a source/drain terminal connected to an operating voltage node (VDD); and a slave latch (230, 241, 300) coupled to the master latch (100), the slave latch (230, 241, 300) configured to receive the master latch output signal (M3) and a second timing signal (nclk) having a second phase, to store digital data (QI) based on the master latch output signal (M3), and to generate a flip flop output signal (QN) based on the master latch output signal (M3), wherein the first timing signal (bclk) is an inverted version of the second timing signal (nclk).
For claim 2, Figure 13 of Kang teaches a transmission gate (220) coupled to the master latch (100) and the slave latch (230, 241, 300), the transmission gate (220) configured to transfer the master latch output signal (M3) from the master latch (100) to the slave latch (230, 241, 300).
For claim 3, Figure 13 of Kang teaches wherein the master latch (100) does not receive the second timing signal (nclk).
For claim 4, Figure 13 of Kang teaches wherein the master latch (100) is a single phase master latch (100) and the first timing signal (bclk) is a single timing signal (bclk) having a single phase.
For claim 5, Figure 13 of Kang teaches wherein the master latch (100) is further configured to receive a serial input signal (SI).
For claim 6, Figure 13 of Kang teaches wherein the first timing signal (bclk) is a doubled inverted clock signal (bclk is doubled inverted of 511-512 in 500).
For claim 16, Figure 13 of Kang teaches a circuit which perform a method of storing data comprising: receiving a data signal (D) and a first timing signal (bclk) having a first phase at a master latch (100), wherein the first timing signal (bclk) is received by first (MP143 inside 145, see Figure 16) and second (MP125 inside 125, see Figure 14) transistors of the master latch, and each of the first and second transistors (MP143 inside 145, see Figure 16; MP125 inside 125, see Figure 14) includes a source/drain terminal connected to an operating voltage node (VDD); generating a master latch output signal (M3) based on the data signal (D) and the first timing signal (bclk); receiving the master latch output signal (M3) and a second timing signal (nclk) having a second phase at a slave latch (230, 241, 300), wherein the second timing signal (nclk) is not received at the master latch (100); and the first timing signal (bclk) is an inverted version of the second timing signal (nclk); storing digital data (QI) in the slave latch (230, 241, 300) based on the master latch output signal (M3); and generating a flip flop output signal (QN) based on the master latch output signal (M3).
For claim 17, Figure 13 of Kang teaches receiving the first timing signal (bclk) at the slave latch (230, 241, 300).
For claim 18, Figure 13 of Kang teaches wherein the first timing signal (bclk) is a doubled inverted clock signal (bclk is doubled inverted of 511-512 in 500).
For claim 19, Figure 13 of Kang teaches wherein the second timing signal (nclk) is an inverted clock signal (inverted clock signal CK, see 500).
For claim 20, Figure 13 (and also see Figures 14 and 16) of Kang teaches wherein the master latch (100 except for 145) includes a plurality of transistors (see Figures 13-14 and 16).
For claim 21, Figure 13 of Kang teaches a circuit comprising: a master latch (100) configured to receive a data signal (D) and a first timing signal (bclk) having to generate a master latch output signal (M3) based on the data signal (D) and the first timing signal (bclk); wherein first and second transistors (MP143 inside 145, see Figure 16; MP125 inside 125, see Figure 14) of the master latch are configured to receive the first timing signal (bclk), and each of the first and second transistors (MP143 inside 145, see Figure 16; MP125 inside 125, see Figure 14) includes a source/drain terminal connected to an operating voltage node (VDD); and a slave latch (230, 241, 300) coupled to the master latch (100), the slave latch (230, 241, 300) configured to receive the master latch output signal (M3) and a second timing signal (nclk) to generate a flip flop output signal (QN) based on the master latch output signal (M3), wherein the first timing signal (bclk) is an inverted version of the second timing signal (nclk).
For claims 22 and 27, Figure 13 of Kang teaches wherein the master latch (100) comprises: a clock gating circuit (125, 160, MN174-MP174, 176) comprising a plurality of clock gating transistors (MN174-MP174, MP163, also see Figure 14), the clock gating circuit (125, 160, MN174-MP174, 176) configured to receive the first timing signal (bclk) and the data signal (D) and to generate a clock gating output signal (output of 160, M2) based on the first timing signal (bclk) and the data signal (D); and a combinational logic circuit (130, 145) coupled to the clock gating circuit (125, 160, MN174-MP174, 176), the combinational logic circuit (130, 145) configured to receive the clock gating output signal (output of 160, M2) and the first timing signal (bclk).
For claim 23, Figure 13 of Kang teaches wherein the clock gating circuit (125, 160, MN174-MP174, 176) receives the first timing signal (bclk) at a PMOS transistors (MP125 of 125 in Figure 14).
For claim 24, Figure 13 of Kang teaches wherein the combinational logic circuit (130, 160) receives the clock gating output signal (output of 160, M2) at a PMOS transistor and an NMOS transistor (PMOS and NMOS inside NOR 130 and/or NAND 145, see Figures 14 and 16).
For claim 25, Figure 13 of Kang teaches wherein the master latch (100) is a single phase master latch (100) and the first timing signal (bclk) is a single timing signal (bclk) having a single phase.
For claim 26, Figure 13 of Kang teaches wherein the first timing signal (bclk) is a doubled inverted clock signal (bclk is doubled inverted of 511-512 in 500).
For claim 28, Figure 13 (and also see Figures 14 and 16) of Kang teaches wherein the first and second transistors (MP143 inside 145, see Figure 16; MP125 inside 125, see Figure 14) of the master latch (100) are both PMOS transistors (MP143 inside 145, see Figure 16; MP125 inside 125, see Figure 14).
For claim 29, Figure 13 (and also see Figures 14 and 16) of Kang teaches wherein the master latch (100) further includes third and fourth transistors (MN174; and MN143 inside 145, see Figure 16), each of the third and fourth transistors (MN174; and MN143 inside 145, see Figure 16) has a gate terminal configured to receive the first timing signal (bclk), the first and second transistors (MP143 inside 145, see Figure 16; MP125 inside 125, see Figure 14) are PMOS transistors (MP143 inside 145, see Figure 16; MP125 inside 125, see Figure 14), and the third and fourth transistors (MN174; and MN143 inside 145, see Figure 16) are NMOS transistors (MN174; and MN143 inside 145, see Figure 16).
Response to Arguments
Applicant's arguments filed 05/20/26 have been fully considered but they are not persuasive.
Applicant argues that “as shown in Fig. 13 of Kang, the asserted first timing signal M3CK is an output of a NAND gate 145 upon receiving the asserted master latch output M3 and a double inverted clock signal bclk, not an inverted version of the asserted second timing signal nclk”. However, this argument is not persuasive because, in Figures 13-16 of Kang, by reading a first timing signal (bclk); the first (MP143 inside 145, see Figure 16) and second (MP125 inside 125, see Figure 14) transistors of the master latch (100); and a second timing signal (nclk), then Kang still teaches all the limitations of the claims as recited.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
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/Long Nguyen/
Primary Examiner
Art Unit 2842
Prosecution Insights