DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in respond to the amendment filed on 12/17/25.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 and 27-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 1, the recitation “the first and second transistors” recited on line 4 lacks antecedent basis. Clarification and/or appropriate correction is required.
Claims 2-7 and 27-28 are indefinite because they depend on claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 16-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (US 2022/0397607).
For claim 1, Figure 13 of Kang teaches a circuit comprising: a master latch (100 except for 145) configured to receive a data signal (D) and a first timing signal (M3CK) having a first phase and to generate a master latch output signal (M3) based on the data signal (D) and the first timing signal (M3CK); wherein the first (MP174) and second (MP163 inside “130,160”, see Figure 14) transistors of the master latch are configured to receive the first timing signal (M3CK), and each of the first (MP174) and second (MP163 inside “130,160”, see Figure 14) transistors includes a source/drain terminal connected to an operating voltage node (VDD); and a slave latch (230, 241, 300) coupled to the master latch (100 except 145), the slave latch (230, 241, 300) configured to receive the master latch output signal (M3) and a second timing signal (nclk) having a second phase, to store digital data (QI) based on the master latch output signal (M3), and to generate a flip flop output signal (QN) based on the master latch output signal (M3).
For claim 2, Figure 13 of Kang teaches a transmission gate (220) coupled to the master latch (100 except 145) and the slave latch (230, 241, 300), the transmission gate (220) configured to transfer the master latch output signal (M3) from the master latch (100 except 145) to the slave latch (230, 241, 300).
For claim 3, Figure 13 of Kang teaches wherein the master latch (100 except 145) does not receive the second timing signal (nclk).
For claim 4, Figure 13 of Kang teaches wherein the master latch (100 except 145) is a single phase master latch (100 except 145) and the first timing signal (M3CK) is a single timing signal (M3CK) having a single phase.
For claim 5, Figure 13 of Kang teaches wherein the master latch (100 except 145) is further configured to receive a serial input signal (SI).
For claim 6, Figure 13 of Kang teaches wherein the first timing signal (M3CK) is a doubled inverted clock signal (M3CK is generated from nclk through 512 and 145).
For claim 7, Figure 13 (and also see Figures 14 for 145, 130,160) of Kang teaches wherein the master latch (100 except for 145) is a PMOS single phase master latch (100 except for 145).
For claim 16, Figure 13 of Kang teaches a circuit which perform a method of storing data comprising: receiving a data signal (D) and a first timing signal (M3CK, bclk) having a first phase at a master latch (100 except for 145), wherein the first timing signal (M3CK, or bclk) is received by first and second transistors (MP174 in Figure 13 and MP163 inside “130,160” in Figure 14) of the master latch, and each of the first and second transistors (MP174 in Figure 13 and MP163 inside “130,160” in Figure 14) includes a source/drain terminal connected to an operating voltage node (VDD); generating a master latch output signal (M3) based on the data signal (D) and the first timing signal ((M3CK, or bclk); receiving the master latch output signal (M3) and a second timing signal (nclk) having a second phase at a slave latch (230, 241, 300), wherein the second timing signal (nclk) is not received at the master latch (100 except for 145) ; storing digital data (QI) in the slave latch (230, 241, 300) based on the master latch output signal (M3); and generating a flip flop output signal (QN) based on the master latch output signal (M3).
For claim 19, Figure 13 of Kang teaches receiving the first timing signal (bclk) at the slave latch (230, 241, 300).
For claim 18, Figure 13 of Kang teaches wherein the first timing signal (M3CK, or bclk) is a doubled inverted clock signal (M3CK is generated from nclk through 512 and 145; while bclk is doubled inverted of 511-512).
For claim 19, Figure 13 of Kang teaches wherein the second timing signal (nclk) is an inverted clock signal (inverted clock signal CK).
For claim 20, Figure 13 (and also see Figures 14) of Kang teaches wherein the master latch (100 except for 145) includes a plurality of transistors (see Figures 13-14).
For claim 21, Figure 13 of Kang teaches a circuit comprising: a master latch (100 except for 145) configured to receive a data signal (D) and a first timing signal (M3CK) having to generate a master latch output signal (M3) based on the data signal (D) and the first timing signal (M3CK); wherein first (MP174) and second (MP163 inside “130,160”, see Figure 14) transistors of the master latch are configured to receive the first timing signal (M3CK), and each of the first (MP174) and second (MP163 inside “130,160”, see Figure 14) transistors includes a source/drain terminal connected to an operating voltage node (VDD); and a slave latch (230, 241, 300) coupled to the master latch (100 except 145), the slave latch (230, 241, 300) configured to receive the master latch output signal (M3) and a second timing signal (nclk) to generate a flip flop output signal (QN) based on the master latch output signal (M3).
For claims 22 and 27, Figure 13 of Kang teaches wherein the master latch (100 except 145) comprises: a clock gating circuit (160, MN174-MP174, 176) comprising a plurality of clock gating transistors (MN174-MP174, MP163, also see Figure 14), the clock gating circuit (160, , MN174-MP174, 176) configured to receive the first timing signal (M3CK) and the data signal (D) and to generate a clock gating output signal (output of 160, M2) based on the first timing signal (M3CK) and the data signal (D); and a combinational logic circuit (130) coupled to the clock gating circuit (160, MN174-MP174, 176), the combinational logic circuit (130) configured to receive the clock gating output signal (output 160, M3CK) and the first timing signal (M3CK, see Figure 14 for 130,160).
For claim 23, Figure 13 of Kang teaches wherein the clock gating circuit (160, MN174-MP174, 176) receives the first timing signal (M3CK) at a PMOS transistors (MP174, or MP163 in Figure 14).
For claim 24, Figure 13 of Kang teaches wherein the combinational logic circuit (130) receives the clock gating output signal (output of 160) at a PMOS transistor and an NMOS transistor (PMOS and NMOS inside NOR 130).
For claim 25, Figure 13 of Kang teaches wherein the master latch (100 except 145) is a single phase master latch (100 except 145) and the first timing signal (M3CK) is a single timing signal (M3CK) having a single phase.
For claim 26, Figure 13 of Kang teaches wherein the first timing signal (M3CK) is a doubled inverted clock signal (M3CK is generated from nclk through 512 and 145).
For claim 28, Figure 13 (and also see Figures 14) of Kang teaches wherein the first (MP174) and second (MP163 inside “130,160”, see Figure 14) transistors of the master latch are both PMOS transistors.
Response to Arguments
Applicant’s arguments filed on 12/17/25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-8101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2842