DETAILED ACTION
This action is responsive to the following communication: the response filed 12/10/2025. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1, 3-11, 13-13 pending.
Claim Objections
The claim(s) is/are objected to because of the following informalities:
Claim 11: it appears that “where k (k is an integer of 2 or greater)” in line(s) 3 was meant to be -- where k is an integer of 2 or greater --.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shikata et al 2017/0337969 ‒hereinafter Shikata).
Regarding claim 1, Shikata discloses a memory device comprising:
a first memory cell (any target memory cell transistor MT0-MT7; fig. 3, para 0050) configured to store multi-bit data (“a multi-level cell (MLC) scheme of storing data of 2 bits or more in each memory cell” para 0048) with a k-value threshold voltage level (Vth; para 0064), where k is an integer of 2 or larger (k = 4 threshold voltages; fig. 4)); and
a sequencer (17; fig. 2) configured to execute a write operation (para 0054) having a loop process (fig. 6, 7) including a program operation (1st/2nd phase programming; fig. 6) and a verify operation (S11/S17; fig. 6), wherein
the program operation includes a first program process (S10; fig. 6) and a second program process (S16; fig. 6), and
the sequencer (17) is further configured to cause the first memory cell (i.e. the targeted memory cell coupled to WLsel) to store data (i.e. any data of data states “A-C”; fig. 4) by either the first program process (S10) or the second program process (S17) according to data to be written (the memory cell is set to be written corresponds to a selected BL; fig. 7) into the first memory cell in the write operation (1st phase stores “A” data, 2nd phase stores data other than “A”, which is verified after programming; fig. 6, 7),
the first memory cell has a first S-factor (any factor enabling an increase in threshold voltage to the “A” data state; fig. 4 para 0058, 0085) in storing the data (“A” data; fig. 4) written by the first program operation (S10; fig. 6), and the first memory cell has a second S-factor (any factor enabling an increase in threshold voltage to remaining data states other than “A” data, i.e. “B-C” data; fig. 4 para 0058, 0085) different from the first S- factor (“A” data) in storing data written by the second program operation (S16; fig. 6).
Regarding claim 5, Shikata discloses the memory device, wherein the k-value threshold voltage level includes first to k-th threshold voltage levels (k = 4 value, i.e. 1st to 4th threshold voltages; fig. 4), and the sequencer is further configured to, in the write operation, in a case of storing the data in the first memory cell by the first program process (S10; fig. 6), write the memory cell at an n-th threshold voltage level (i.e. 2nd threshold voltage level; fig. 4), wherein n is an even number and an integer of 2 or larger and k or smaller (n = 2), and in a case of storing the data in the first memory cell by the second program process (S16; fig. 6), write the memory cell at an m-th threshold voltage level (i.e. 3rd threshold voltage level; fig. 4), where m is an odd number and an integer of 3 or larger and k or smaller (m = 3).
Regarding claim 6, Shikata discloses the memory device, wherein: the verify operation includes a first verify read (S11; fig. 6, further first verify read corresponds to verify in 1st phase; fig. 7) and a second verify read (S17; fig. 6, further second verify read corresponds to verify in 2nd phase; fig. 7), the first verify read being associated with a write of data corresponding to the n-th threshold voltage level (i.e. 2nd threshold voltage level; fig. 4) and the second verify read being associated with a write of data corresponding to an (n+1)-th threshold voltage level (i.e. 3rd threshold voltage level; fig. 4), and the sequencer is further configured to collectively execute the first verify read and the second verify read using the same verify voltage (i.e. BV/CV in the first and second verify reads are the same verify voltage; fig. 7).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4, 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shikata et al 2017/0337969 ‒hereinafter Shikata) in view of Kamata et al. (US 2020/0135271 ‒hereinafter Kamata).
Regarding claim 3, Shikata discloses the memory device, wherein the sequencer is further configured to use a first sense time in reading the data written (in a read operation, a sense time at which signal STB is asserted corresponding to verify; fig. 7, para 0081, 0096) by the first program process (S10; fig. 6) from the first memory cell, and to use a second sense time in reading the data written (in the read operation, another sense time at which signal STB is asserted corresponding to verify; fig. 7, para 0081, 0096) by the second program process (S16; fig. 6) from the first memory cell.
Shikata does not expressly disclose a second sense time different from the first sense time
Kamata discloses a second sense time (T15-T16; fig. 8) different (i.e. performed at different sense times; fig. 8) from the first sense time (T12-T13; fig. 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Shikata is modifiable as taught by Kamata for the purpose of achieving accurate readout results while reducing readout latency (para 0120 of Kamata), which predicts the commonly understood advantage of efficiently performing data accessing schemes.
Regarding claim 4, Shikata discloses the memory device, further comprising: a sense amplifier (SAU; fig. 5) connected to the first memory cell (i.e. the targeted memory cell coupled to BL) and having a sense node (SEN; fig. 5).
Shikata does not expressly disclose wherein each of the first sense time and the second sense time is associated with a time during which a read voltage is applied to the first memory cell from electrical connection between the sense node and the first memory cell to electrical disconnection between the sense node and the first memory cell, and the first sense time is different from the second sense time.
Kamata discloses wherein each of the first sense time and the second sense time is associated with a time (SENSE PERIOD; fig. 8) during which a read voltage (VA/VC; fig. 8) is applied to the first memory cell (i.e. via selected word line WL; fig. 8) from electrical connection between the sense node (SEN; fig. 6) and the first memory cell (i.e. via bit line BL; fig. 6) (para 0103) to electrical disconnection between the sense node (SEN) and the first memory cell (i.e. via bit line BL) (para 0114), and the first sense time (T12-T13; fig. 8) is different (i.e. performed at different sense times; fig. 8) from the second sense time (T15-T16; fig. 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Shikata is modifiable as taught by Kamata for the purpose of achieving accurate readout results while reducing readout latency (para 0120 of Kamata), which predicts the commonly understood advantage of efficiently performing data accessing schemes.
Regarding claim 7, Shikata, in an embodiment, discloses the memory device, wherein in the verify operation, the sequencer executes a verify read (para 0165-0166) in each of a case where the first memory cell is a target (i.e. memory cell targeted for first programming; para 0091) of the first program process (S10; fig. 6) and a case where the first memory cell is a target (i.e. memory cell targeted for second programming; para 0100) of the second program process (S16; fig. 6).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Shikata is modifiable as taught for the purpose of facilitating data accessing schemes by providing optimal threshold voltage distributions which improves the reliability of data storage (para 0168-0171 of Shikata).
Kamata discloses using a first sense time (T12-T13; fig. 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Shikata is further modifiable as taught by Kamata for the purpose of achieving accurate readout results while reducing readout latency (para 0120 of Kamata), which predicts the commonly understood advantage of efficiently performing data accessing schemes.
Regarding claim 8, Shikata, in an embodiment, discloses the memory device, wherein in the verify operation, the sequencer is configured to: execute a verify read (para 0165-0166) in a case where the first memory cell is a target (i.e. memory cell targeted for first programming; para 0091) of the first program process (S10; fig. 6); and execute a verify read (para 0165-0166) in a case where the first memory cell is a target (i.e. memory cell targeted for second programming; para 0100) of the second program process (S16; fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Shikata is modifiable as taught for the purpose of facilitating data accessing schemes by providing optimal threshold voltage distributions which improves the reliability of data storage (para 0168-0171 of Shikata).
Shikata does not expressly disclose using the first sense time; using a second sense time.
Kamata discloses using a first sense time (T12-T13; fig. 8); using a second sense time (T15-T16; fig. 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Shikata is further modifiable as taught by Kamata for the purpose of achieving accurate readout results while reducing readout latency (para 0120 of Kamata), which predicts the commonly understood advantage of efficiently performing data accessing schemes.
Regarding claim 9, Shikata discloses the memory device, further comprising: a sense amplifier (SAU; fig. 5) connected to the first memory cell (i.e. the targeted memory cell coupled to BL), the sense amplifier having a sense node (SEN; fig. 5).
Shikata does not expressly disclose wherein: each of the first sense time and the second sense time is associated with a first time, the first time is associated with a time during which a read voltage is applied to the first memory cell from electrical connection between the sense node and the first memory cell to electrical disconnection between the sense node and the first memory cell, and the first sense time is different from the second sense time.
Kamata discloses wherein each of the first sense time and the second sense time is associated with a first time (TIME; fig. 8), the first time is associated with a time (SENSE PERIOD; fig. 8) during which a read voltage (VA/VC; fig. 8) is applied to the first memory cell (i.e. via selected word line WL; fig. 8) from electrical connection between the sense node (SEN; fig. 6) and the first memory cell (i.e. via bit line BL; fig. 6) (para 0103) to electrical disconnection between the sense node (SEN) and the first memory cell (i.e. via bit line BL) (para 0114), and the first sense time (T12-T13; fig. 8) is different (i.e. performed at different sense times; fig. 8) from the second sense time (T15-T16; fig. 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Shikata is modifiable as taught by Kamata for the purpose of achieving accurate readout results while reducing readout latency (para 0120 of Kamata), which predicts the commonly understood advantage of efficiently performing data accessing schemes.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shikata et al 2017/0337969 ‒hereinafter Shikata) in view of Joe (US 2023/0145681).
Regarding claim 10, Shikata discloses the memory device, further comprising: a second memory cell and a third memory cell that are connected in series with the first memory cell and are adjacent to the first memory cell (fig. 3), wherein the sequencer is further configured to: in the first program process (S10; fig. 6) for the first memory cell, apply a program voltage (Vpgm; fig. 7) to the first memory cell, apply a first voltage (Vpass; fig. 7) to the second memory cell (i.e. coupled to WLusel; fig. 7), and in the second program process (S16; fig. 6) for the first memory cell, apply the program voltage to the first memory cell (Vpgm (+ΔVpgm2); fig. 7), and apply the third voltage (Vpass (+ΔVpass2); fig. 7) to the third memory cell (i.e. coupled to WLusel; fig. 7).
Shikata does not expressly disclose apply a third voltage to the third memory cell, apply a fourth voltage lower than the first voltage to the second memory cell.
Joe discloses apply a third voltage (V1/V2; fig. 15) to the third memory cell (i.e. coupled to WLn+1/WLn-1; fig. 15-16), apply a fourth voltage lower (V3/V4; fig. 15-16) than the first voltage to the second memory cell (i.e. coupled to WLn+1/WLn-1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of facilitating data accessing schemes by controlling biasing to word lines to reduce program disturbances that may otherwise hinder a complex operating system (para 0004 of Joe).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shikata et al 2017/0337969 ‒hereinafter Shikata) in view of Dutta et al. (US 2014/0160848 ‒hereinafter Dutta).
Regarding claim 11, Shikata discloses a memory device comprising:
a memory cell (any target memory cell transistor MT0-MT7; fig. 3, para 0050) configured to store multi-bit data (“a multi-level cell (MLC) scheme of storing data of 2 bits or more in each memory cell” para 0048) with a k-value threshold voltage level (Vth; para 0064), where k is an integer of 2 or greater (k = 4 threshold voltages; fig. 4);
a select transistor (ST1/ST2; fig. 3) connected to the memory cell (i.e. target memory cell);
a bit line connected (any target bit line BL0-BL(L-1); fig. 3) to the select transistor (ST1/ST2); and
a sequencer (17; fig. 2) configured to: execute a write operation (para 0054) having a first program operation (S10; fig. 6, 7) and a loop process (2nd phase; fig. 6, 7), the loop process including a second program operation (S15; fig. 6) and a verify operation (S17; fig. 6),
in the first program operation (S10) in which the memory cell is a program target (i.e. memory cell targeted for first programming; para 0091), applying a first program voltage (Vpgm applied to WLsel; fig. 7) to the memory cell (i.e. the targeted memory cell coupled to WLsel),
in the second program operation (S15) in which the memory cell is a program target (i.e. memory cell targeted for second programming; para 0100), applying a second program voltage (Vpgm+ΔVpgm2; fig. 7) to the memory cell (i.e. the targeted memory cell coupled to WLsel),
in the write operation, execute the first program operation (S10) with the memory cell (i.e. the targeted memory cell coupled to WLsel) set to be written (the memory cell is set to be written corresponds to a selected BL; fig. 7) or be write-inhibited (the memory cell is set to be write-inhibited corresponds to an inhibited BLinh; fig. 7) according to data to be written in the memory cell (i.e. any data of data states “A-C”; fig. 4), and store the data in the memory cell by the loop process (the loop process, i.e. 2nd phase, stores data other than “A”, which is verified after programming; fig. 6, 7),
the first memory cell has a first S-factor (any factor enabling an increase in threshold voltage to the “A” data state; fig. 4 para 0058, 0085) in storing the data (“A” data; fig. 4) written by the first program operation (S10; fig. 6), and the first memory cell has a second S-factor (any factor enabling an increase in threshold voltage to remaining data states other than “A” data, i.e. “B-C” data; fig. 4 para 0058, 0085) different from the first S- factor (“A” data) in storing data written by the second program operation (S16; fig. 6).
Shikata does not expressly disclose apply a first voltage to the select transistor while applying a first program voltage; apply a second voltage lower than the first voltage to the select transistor while applying a second program voltage.
Dutta discloses apply (820; fig. 8) a first voltage to the select transistor (Vgs is applied to a select transistor; para 0090) while applying a first program voltage (programming voltage pulse Vpgm; para 0091); apply (836; fig. 8) a second voltage lower than the first voltage (a lower Vgs is applied to the select transistor; para 0098) to the select transistor while applying a second program voltage (a stepped up programming pulse Vpgm; para 0099).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Shikata is modifiable as taught by Dutta for the purpose of preventing unintentional biasing of select transistors, which facilitates data accessing schemes and reduces disturbances that may otherwise hinder a complex operating system (para 0047 of Dutta).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shikata et al 2017/0337969 ‒hereinafter Shikata) in view of Dutta et al. (US 2014/0160848 ‒hereinafter Dutta), and further in view of Harari et al. (US 2008/0116509 ‒hereinafter Harari).
Regarding claim 13, Shikata, as modified, does not expressly disclose the memory device, wherein: the memory cell has a first floating gate portion and a second floating gate portion, the first program operation is a program operation for the second floating gate portion, and the second program operation is a program operation for the first floating gate portion.
Harari discloses wherein the memory cell has a first floating gate portion and a second floating gate portion (i.e. dual floating gate; para 0018), the first program operation is a program operation for the second floating gate portion, and the second program operation is a program operation for the first floating gate portion (“Two or more such charge levels, and thus two or more different threshold levels, are defined for programming into each of the two charge storage regions of each memory cell” para 0018).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Shikata is further modifiable as taught by Harari for the purpose of facilitating data accessing schemes by extending a lifetime of the memory device (para 0017 of Herari), which predicts the commonly understood advantage of having a robust and high endurance device.
Regarding claim 14, Shikata, as modified, does not expressly disclose the memory device, wherein: in the first program operation, electrons are injected into the second floating gate portion using hot electrons, and in the second program operation, electrons are injected into the first floating gate portion using a Fowler-Nordheim (FN) tunnel current.
Herari, in an embodiment, discloses wherein in the first program operation (para 0108), electrons are injected into the second floating gate portion (charge storage portion; para 0107) using hot electrons (hot-electron injection; para 0107), and in the second program operation (para 0108), electrons are injected into the first floating gate portion (another charge storage region; para 0107) using a Fowler-Nordheim (FN) tunnel current (Fowler-Nordhein tunneling; para 0107).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Shikata is further modifiable as taught by Harari for the purpose of facilitating data accessing schemes by extending a lifetime of the memory device (para 0017 of Herari), which predicts the commonly understood advantage of having a robust and high endurance device.
Response to Arguments
Applicant's arguments filed 12/10/2025 have been fully considered but are not persuasive.
The applicant submits that Shikata fails to disclose different S-factors as required (on page 3 of the response, regarding the pending claim(s)).
The examiner respectfully disagrees with the arguments. Currently, claims 1 and 11 recites the first memory cell having different S-factors for different program processes; however, the claims and dependent claims does not provide limitations to further define the S-factors. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Therefore, it is reasonable to interpret that S-factors include any element to facilitate storing of data in the first memory cell by the first and second program process, not necessarily involving “selective trapping of electrons in regions between adjacent memory cells” as submitted.
Shikata teaches the first program storing a first state corresponding to a threshold voltage, and the second program storing remaining state(s) corresponding to a threshold voltage (fig. 4, 6). Further, in “the program operation, by applying a program voltage to the word line WL, electrons are injected into a charge storage layer of the memory cell transistor MT, and thus the threshold voltage of the memory cell transistor MT increases” (para 0085). The first program process enables an increase in threshold voltage to data state “A”, therefore is considered to have a S-factor corresponding to the data state; the second program process enables an increase in threshold voltage to remaining data state(s) “B-C”, therefore is considered to have another, different, S-factor corresponding to the remaining data state(s).
For at least the aforementioned reasons, the rejection is deemed proper and made final.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/UYEN SMET/
Primary Examiner, Art Unit 2824
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