DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I, sub-species a in the reply filed on 6/3/2026 is acknowledged. The traversal is on the ground(s) that figures 5A and 5B are horizontal cross sections of the first source and drain and thus the restriction requirement appears to be premature. This is found persuasive and the restriction between Species I and II is hereby withdrawn.
Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected sub-species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 6/3/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 11, it is unclear how a width of the first gate structure can be greater than a width of the first gate structure.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 12-14, 16 and 18-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LIN et al. (US PG Pub 2023/0307456, hereinafter Lin).
Regarding claim 1, figures 1A-1D of Lin disclose an integrated circuit semiconductor device comprising:
a first transistor (105) comprising a first nano-sheet stack structure (107), a first gate structure (113), and a first source and drain (117), the first transistor having a first horizontal direction, a second horizontal direction perpendicular to the first horizontal direction, and a vertical direction perpendicular to the first horizontal direction and the second horizontal direction; and
a second transistor (104) comprising a second nano-sheet stack structure (106), a second gate structure (112), and a second source and drain (116), the second transistor being separated from the first transistor by a transistor isolation insulating layer (129) in the vertical direction,
wherein the first nano-sheet stack structure comprises a plurality of first nano-sheet stacks (107) spaced apart from each other in the first horizontal (X) direction, wherein each of the plurality of first nano-sheet stacks comprises a plurality of first nano-sheets stacked in the vertical direction,
wherein the first gate structure extends in the second horizontal (Y) direction and surrounds the first nano-sheet stack structure in the vertical direction,
wherein the first source and drain (117) is disposed on both sides of at least one first nano-sheet stack in the first horizontal direction,
wherein the second nano-sheet stack structure comprises a plurality of second nano-sheet stacks (106) spaced apart from each other in the first horizontal direction,
wherein each of the plurality of second nano-sheet stacks comprises a plurality of second nano-sheets (106) stacked in the vertical direction, and
wherein the second gate structure (112) extends in the second horizontal direction and surrounds the second nano-sheet stack structure in the vertical direction,
wherein the second source and drain (116) is disposed on both sides of at least one second nano-sheet stack in the first horizontal direction.
Regarding claim 2, figures 1A-1D of Lin disclose the first transistor and the second transistor comprise different types of transistors (¶ 26).
Regarding claim 3, figure 2M of Lin discloses a channel length of the first transistor (105) is different from a channel length of the second transistor (107) (due to the date electrodes 113 and 112 having different widths).
Regarding claim 4, figures 1A-1D of Lin disclose the transistor isolation insulating layer comprises a gate isolation insulating layer (129) separating the first gate structure (113) and the second gate structure (112) from each other in the vertical direction.
Regarding claim 5, figures 1A-1D of Lin disclose the transistor isolation insulating layer comprises a source and drain isolation insulating layer (128) separating the first source and drain (117) and the second source and drain (116) from each other in the vertical direction.
Regarding claim 6, figures 1A-1D of Lin disclose a first metal wiring layer (125) connected in an inverse vertical direction to the first source and drain (117); and
a second metal wiring layer (124) connected in the vertical direction to the second source and drain (116).
Regarding claim 7, figures 1A-1D of Lin disclose the first source and drain and the second source and drain comprise epitaxial layers doped with impurities (¶ 92-95).
Regarding claim 12, figures 1A-1D of Lin disclose an integrated circuit semiconductor device comprising:
a first transistor (104) comprising a first nano-sheet stack structure (106), a first gate structure (112), and a first source and drain (116), the first transistor having a first horizontal direction, a second horizontal direction perpendicular to the first horizontal direction, and a vertical direction perpendicular to the first horizontal direction and the second horizontal direction; and
a second transistor (105) comprising a second nano-sheet stack structure (107), a second gate structure (113), and a second source and drain (117), the second transistor being separated from the first transistor by a transistor isolation insulating layer (129) in the vertical direction,
wherein the first nano-sheet stack structure comprises a plurality of first nano-sheet stacks spaced apart from each other in the first horizontal direction (X), wherein each of the plurality of first nano-sheet stacks comprises a plurality of first nano-sheets (106) stacked in the vertical direction,
wherein the first gate structure extends in the second horizontal direction (Y) and surrounds the first nano-sheet stack structure in the vertical direction,
wherein the first source and drain (116) is disposed on both sides of at least one first nano-sheet stack structure in the first horizontal direction,
wherein the second nano-sheet stack structure comprises a plurality of second nano-sheet stacks spaced apart from each other in the first horizontal direction, wherein each of the plurality of second nano-sheet stacks comprises a plurality of second nano-sheets (107) stacked in the vertical direction,
wherein the second gate structure (113) extends in the second horizontal direction and surrounds the second nano-sheet stack structure in the vertical direction,
wherein the second source and drain (117) is disposed on both sides of at least one second nano-sheet stack in the first horizontal direction,
wherein the transistor isolation insulating layer comprises a gate isolation insulating layer (129) separating the first gate structure and the second gate structure in the vertical direction, and a source and drain isolation insulating layer (128) separating the first source and drain and the second source and drain in the vertical direction; and
wherein a height of the second source and drain (117) is greater than or equal to a height of the first source and drain (116).
Regarding claim 13, figures 1A-1D of Lin disclose a first metal wiring layer (124) connected in an inverse vertical direction to the first source and drain (116); and
a second metal wiring layer (125) connected in the vertical direction to the second source and drain (117).
Regarding claim 14, figures 1A-1D of Lin disclose the first source and drain (116), and the second source and drain (117) comprise epitaxial layers doped with impurities (¶ 92-95).
Regarding claim 16, figures 1A-1D of Lin disclose an integrated circuit semiconductor device comprising:
a transistor isolation insulating layer (129) having a first horizontal direction, a second horizontal direction perpendicular to the first horizontal direction, and a vertical direction perpendicular to the first horizontal direction and the second horizontal direction;
a first transistor (105) arranged under the transistor isolation insulating layer in an inverse vertical direction, the first transistor comprising a first nano-sheet stack structure (107), a first gate structure (113), a first source and drain (117), and a first metal wiring layer (125); and
a second transistor (104) arranged under the transistor isolation insulating layer in the vertical direction, the second transistor comprising a second nano-sheet stack structure (106), a second gate structure (112), a second source and drain (116), and a second metal wiring layer (124),
wherein the first nano-sheet stack structure comprises a plurality of first nano-sheet stacks spaced apart from each other in the first horizontal direction (X), wherein each of the plurality of first nano-sheet stacks comprises a plurality of first nano-sheets (107) stacked in the vertical direction,
wherein the first gate structure extends in the second horizontal direction (Y) and surrounds the first nano-sheet stack structure in the vertical direction,
wherein the first source and drain (117) is disposed on both sides of at least one first nano-sheet stack in the first horizontal direction,
wherein the first metal wiring layer (125) is connected to the first source and drain (117) in the inverse vertical direction,
wherein the second nano-sheet stack structure comprises a plurality of second nano-sheet stacks spaced apart from each other in the first horizontal direction, wherein each of the plurality of second nano-sheet stacks (106) comprises a plurality of second nano-sheets stacked in the vertical direction,
wherein the second gate structure extends in the second horizontal direction and surrounds the second nano-sheet stack structure in the vertical direction,
wherein the second source and drain (116) is disposed on both sides of at least one second nano-sheet stack in the first horizontal direction, and
wherein the second metal wiring layer (124) is connected to the second source and drain in the vertical direction.
Regarding claim 18, figures 1A-1D of Lin disclose each of the first metal wiring layer (125) and the second metal wiring layer (124) comprise a power line or a signal line.
Regarding claim 19, figures 1A-1D of Lin disclose the first gate structure comprises a first gate insulating layer (108) and a first gate metal layer (113), and the second gate structure comprises a second gate insulating layer (110) and a second gate metal layer (112), and the first gate insulating layer and the second gate insulating layer are separated from each other in the vertical direction.
Allowable Subject Matter
Claims 8-10, 15, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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