Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 (Fig. 2) in the reply filed on 5/22/2026 is acknowledged.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Allowable Subject Matter
Claims 3, 16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3: The following is an examiner’s statement of reasons for allowance: The primary reason for the allowance of the claims is the inclusion of the limitation “wherein the first lightly doped region includes P-type impurity, the second lightly doped region includes N-type impurity, the first lightly doped region and the second lightly doped region form a PN junction, and the second lightly doped region is positioned closer to the gate electrode than the first lightly doped region”, in all of the claims which is not found in the prior art references.
Claims 16 and 20 contain similar language.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 2, 4-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bauer et al. (US 20110117732 A1) in view of Chang et al. (US 20230261092 A1).
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Claim 1. Bauer teaches a semiconductor device, comprising: a semiconductor substrate including a plurality of trenches and silicon (Bauer ¶101); a gate electrode 122 positioned on the semiconductor substrate and between the trenches; and a source region and a drain region respectively positioned within the trenches, wherein the source region 114 and the drain region 114 include SiC or GaN (Bauer claim 17), the source region and the drain region each includes a first doped region and a second doped region, a whole of the first doped region overlaps the second doped region in a direction perpendicular to an upper surface of the semiconductor substrate (Bauer Fig. 2G).
Bauer is silent regarding the relative doping of the source/drain (S/D) layers, disclosing only that they may differ. A Person Having Ordinary Skill in the Art (PHOSITA) looking to form the device would naturally look to known doping arrangements.
Chang teaches a multi-level doping arrangement for transistors, which may include first and second lightly doped regions (e.g., LDD). As shown in Fig. 4 of Chang, a transistor S/D region could include overlapping LDD regions and an additional S/D layer with a relatively higher doping concentration, a configuration well known and utilized in the art by a PHOSITA.
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It would have been obvious to a PHOSITA at the time of the invention to modify Bauer's doping profile with the known doping profile demonstrated in Chang. Applying a known technique to a known device ready for improvement to yield predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc.), particularly when the modification solves a predictable design challenge inherent to Bauer's broad disclosure.
Claim 2. Bauer in view of Chang teach the semiconductor device of claim 1, Buaer teaches Silicon Carbide but is however silent upon wherein the SiC includes at least one of 4H-SIC, 6H-SIC, or 3C-SiC. The selecting of a specific silicon carbide polytype (4H-SiC, 6H-SiC, or 3C-SiC) is obvious to a PHOSITA in view of In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
These polytypes represent a limited number of common, commercially available, and predictable alternatives in semiconductor manufacturing. A PHOSITA would routinely select among them based on known substrate configurations and engineering trade-offs. For example, a PHOSITA would predictable select cubic 3C-SiC for silicon substrates to reduce lattice mismatch, or hexagonal 4H-SiC/6H-SiC for hexagonal substrates to achieve homoepitaxial growth.
Because choosing a specific known polytype to match a substrate structure represents nothing more than a routine selection from a pool of known materials to achieve a predictable result, it constitutes a mere choice of design variables. Consequently, specifying 4H-SiC, 6H-SiC, or 3C-SiC provides no patentable distinction.
Claim 4. Bauer in view of Chang teach the semiconductor device of claim 1, wherein doping concentration of each of the first lightly doped region and the second lightly doped region is in a range from about 10.sup.15 cm.sup.−3 to about 10.sup.17 cm.sup.−3 (Chang ¶20 – As taught in Change, the ranged known ranges routinely selected to optimize device parameters.).
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the concentration levels through routine experimentation and optimization to obtain optimal or desired device performance because the concentration is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
Claim 5. Bauer in view of Chang teach the semiconductor device of claim 1, wherein the semiconductor substrate further comprises a second impurity doped region positioned between the source region and the gate electrode, and between the drain region and the gate electrode (Bauer Fig. 2g & Chang fig. 4 – Note: This limitation does not clearly or explicitly define a particular location or establish that the element is distinct from the first and second lightly doped source/drain (S/D) regions because the phrase "between the source region and the gate electrode" encompasses the entire area under the gate. Under BRI, because the lightly doped regions also span this exact space, this language is not limited to a specific sub-region and overlaps structurally with the lightly doped regions.).
Claim 6. Bauer in view of Chang teach the semiconductor device of claim 5, wherein the second impurity doped region includes N-type impurity, doping concentration of the second impurity doped region is in a range from about 10.sup.15 cm.sup.−3 to about 10.sup.17 cm.sup.−3 (Chang ¶20 – As taught in Change, the ranged known ranges routinely selected to optimize device parameters.).
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the concentration levels through routine experimentation and optimization to obtain optimal or desired device performance because the concentration is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable
Claim 7. Bauer in view of Chang teach the semiconductor device of claim 1, further comprising: a second heavily doped region positioned within the second lightly doped region, wherein the second heavily doped region has a doping concentration higher than that of the second lightly doped region (Chang Fig. 4 – Upper S/D layer located over LDD1 and LDD2.)
Claim 8. Bauer in view of Chang teach the semiconductor device of claim 7, further comprising: an interlayer insulating layer positioned above the source region, the gate electrode and the drain region; and a source contact and a drain contact positioned above the interlayer insulating layer, wherein the interlayer insulating layer includes a first opening overlapping the source region and a second opening overlapping the drain region, the second heavily doped region of the source region is in direct contact with the source contact at the first opening, the second heavily doped region of the drain region and the drain contact are in direct contact at the second opening.
Claim 9. Bauer in view of Chang teach the semiconductor device of claim 1, further comprising: an isolation layer STI positioned within the semiconductor substrate and defining a plurality of active regions; and an isolation impurity region positioned below the isolation layer, wherein the isolation impurity region includes P-type impurity (Bauer Fig. 2G – The phrase "Wherein the isolation impurity region includes P-type impurity" is a functional limitation that reads directly on Bauer. Bauer discloses a transistor that operates in either P or N-channel configurations. For a P-channel transistor, Bauer's substrate structure structurally meets the scope of the claims, making the functional addition of a "P-type impurity region" merely a descriptive property of Bauer's inherently present structure.).
Claim 10. Bauer in view of Chang teach the semiconductor device of claim 1, may be silent upon” wherein a depth of each of the trenches is in a range from about 100 nm to about 1000 nm”. It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the depth through routine experimentation and optimization to obtain optimal or desired device performance because the depth is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Claim 11. Bauer in view of Chang teach the semiconductor device of claim 1, wherein an upper surface of each of the source region and the drain region has a shape in which an area on a plane becomes narrower toward the top (Bauer Fig. 2G & Chang fig. 4).
Claim 12. Bauer in view of Chang teach the semiconductor device of claim 1, wherein an area on a plane for each of the source region and the drain region at an upper surface and an area on a plane for each of the source region and the drain region at a lower surface have a same size (Bauer Fig. 2G & Chang fig. 4).
Claim 13. Bauer in view of Chang teach the semiconductor device of claim 1, wherein top surfaces of the source region and the drain region protrude from the upper surface of the semiconductor substrate (Bauer Fig. 2G & Chang fig. 4).
Claim 14. Bauer in view of Chang teach the semiconductor device of claim 1, wherein in the source region and the drain region, a thickness of the first lightly doped region is thicker than a thickness of the second lightly doped region (Bauer Fig. 2G & Chang fig. 4).
Claim(s) 15, 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bauer et al. (US 20110117732 A1) in view of Chang et al. (US 20230261092 A1) in view of Huo (US 20190157298 A1).
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Claim 15. Bauer teaches a semiconductor device, comprising: a semiconductor substrate including a plurality of trenches and silicon (Bauer ¶102); a gate electrode 122 positioned on the semiconductor substrate and between the trenches; and a source region and a drain region respectively positioned within the trenches, wherein the source region 114 and the drain region 114 include SiC or GaN (Bauer claim 17), the source region and the drain region each includes a first doped region and a second doped region, a whole of the first doped region overlaps the second doped region in a direction perpendicular to an upper surface of the semiconductor substrate (Bauer Fig. 2G).
Bauer is silent regarding the relative doping of the source/drain (S/D) layers, disclosing only that they may differ. A Person Having Ordinary Skill in the Art (PHOSITA) looking to form the device would naturally look to known doping arrangements.
Chang teaches a multi-level doping arrangement for transistors, which may include first and second lightly doped regions (e.g., LDD). As shown in Fig. 4 of Chang, a transistor S/D region could include overlapping LDD regions and an additional S/D layer with a relatively higher doping concentration, a configuration well known and utilized in the art by a PHOSITA.
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It would have been obvious to a PHOSITA at the time of the invention to modify Bauer's doping profile with the known doping profile demonstrated in Chang. Applying a known technique to a known device ready for improvement to yield predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc.), particularly when the modification solves a predictable design challenge inherent to Bauer's broad disclosure.
While Bauer and Chang acknowledge the known transistor structure, they do not disclose conventional memory circuitry. However, a person having ordinary skill in the art (PHOSITA) would find it obvious to apply this transistor in a peripheral driving and control circuit, as such circuits conventionally utilize higher threshold-type transistors.
Furthermore, Hou et al. teaches that analogous epitaxial source/drain (S/D) transistors are indeed used in the peripheral circuitry of memory cell devices (e.g., Hou, Fig. 8). Because Hou explicitly demonstrates the known convention and use of these transistors in peripheral contexts, modifying the device of Hou with the transistor of Bauer and Chang would have been obvious.
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Ultimately, this modification represents nothing more than the predictable result of substituting one known element for another, a practice KSR recognizes as inherently obvious to a PHOSITA (KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385).
Claim 17. Bauer in view of Chang in view of Huo teach the semiconductor device of claim 15, wherein the semiconductor substrate further comprises a second impurity doped region positioned between the source region and the gate electrode, and between the drain region and the gate electrode (Bauer Fig. 2g & Chang fig. 4 – Note: This limitation does not clearly or explicitly define a particular location or establish that the element is distinct from the first and second lightly doped source/drain (S/D) regions because the phrase "between the source region and the gate electrode" encompasses the entire area under the gate. Under BRI, because the lightly doped regions also span this exact space, this language is not limited to a specific sub-region and overlaps structurally with the lightly doped regions.).
Claim 18. Bauer in view of Chang in view of Huo teach the semiconductor device of claim 15, wherein top surfaces of the source region and the drain region protrude from the upper surface of the semiconductor substrate (Bauer Fig. 2G & Chang fig. 4).
Claim 19. An electronic system, comprising: a semiconductor substrate including a plurality of trenches and silicon; a gate electrode positioned on the semiconductor substrate and between the trenches; and a source region and a drain region respectively positioned within the trenches, wherein the source region and the drain region include SiC or GaN, the source region and the drain region each includes a first lightly doped region and a second lightly doped region, a whole of the first lightly doped region overlaps the second lightly doped region in a direction perpendicular to an upper surface of the semiconductor substrate.
he claimed memory device, encompassing a main substrate, semiconductor devices with peripheral circuits, stacked cell array structures, and corresponding controllers, would have been obvious to a PHOSITA.
First, Bauer and Chang teach a known semiconductor device architecture, while Hou et al. disclose analogous epitaxial source/drain transistors conventionally utilized in memory cell peripheral circuitry. Second, Bauer and Chang may be silent on the specific integration of these high threshold-type transistors into the conventional peripheral driving structures for the claimed three-dimensional memory cells. A PHOSITA possesses the creative capacity to combine these known references, recognizing that peripheral control circuits historically require higher threshold-type transistors for stable driving logic. A PHOSITA would find it obvious to apply the Bauer and Chang transistor structures within the peripheral circuitry of the Hou et al. device, as Hou expressly demonstrates the use of analogous transistors in these exact peripheral contexts MPEP 2143. Finally, this modification constitutes nothing more than the predictable result of substituting one known element for another, a practice recognized by the Supreme Court as inherently obvious to a skilled artisan (KSR Int'l Co. v. Teleflex Inc.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
6/9/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Bauer - [0010] In one embodiment, a method for selectively forming silicon-containing material in a recess is provided. A substrate including a recess is introduced, whereby a pulse of silicon-containing source vapor is used to deposit silicon-containing material in the recess. A continuous etchant flow of one or more vapor-phase etchants is provided to remove portions of the deposited silicon-containing material from the recess. Additional pulses of silicon-containing sources may be introduced repeatedly to deposit silicon-containing material in the recess.
2 Bauer - [0010] In one embodiment, a method for selectively forming silicon-containing material in a recess is provided. A substrate including a recess is introduced, whereby a pulse of silicon-containing source vapor is used to deposit silicon-containing material in the recess. A continuous etchant flow of one or more vapor-phase etchants is provided to remove portions of the deposited silicon-containing material from the recess. Additional pulses of silicon-containing sources may be introduced repeatedly to deposit silicon-containing material in the recess.
Prosecution Insights