DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2, claims 1-5 and 7-20 in the reply filed on August 26, 2026 is acknowledged. Claim 6 has been withdrawn. Action on the merits is as follows:
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 8, 10-12, 15, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MUTO (US 2021/0015006 A1).
In regards to claim 1, MUTO (Figs. 1-3 and associated text) discloses a semiconductor memory module (Figs. 1-3) comprising: a first substrate (item 21) including a first corner; first semiconductor packages (items 27, 28) mounted on a lower surface of the first substrate (item 21, paragraph 57); a second substrate (item 22) disposed over the first substrate (item 21) and including a second corner corresponding to the first corner; second semiconductor packages (item 31) mounted on an upper surface of the second substrate (item 22); and a fixing structure (corner structure of item 11, shown but not labeled) in which the first corner and the second corner are fitted.
In regards to claim 2, MUTO (Figs. 1-3 and associated text) discloses wherein the first substrate (item 21) includes a first plurality of corners including the first corner, wherein the second substrate (item 22) includes a second plurality of corners including the second corner, wherein the fixing structure (corner structure of item 11, shown but not labeled) is a first fixing structure, and the semiconductor memory module (Figs. 1-3) comprises a plurality of fixing structures (corner structures of item 11, shown but not labeled) including the first fixing structure, and wherein each fixing structure (corner structure of item 11, shown but not labeled) of the plurality of fixing structures (corner structures of item 11, shown but not labeled) physically supports corresponding corners of the first plurality of corners and the second plurality of corners.
In regards to claim 3, MUTO (Figs. 1-3 and associated text) discloses wherein the first substrate (item 21) has a first side surface, wherein the second substrate (item 22) has a second side surface disposed over the first side surface, and wherein the semiconductor memory module (Figs. 1-3) further includes at least one first flexible connector (items FP1 or FP2) connecting the first side surface and the second side surface.
In regards to claim 4, MUTO (Figs. 1-3 and associated text) discloses wherein each of the first side surface and the second side surface has a recessed portion, and wherein the first flexible connector (items FP1 or FP2) is disposed in the recessed portion.
In regards to claim 5, MUTO (Figs. 1-3 and associated text) discloses wherein the first flexible connector (items FP1 or FP2) includes: a first flexible layer and a second flexible layer sequentially stacked; a first flexible wiring interposed between the first flexible layer and the second flexible layer; and an active element interposed between the first flexible layer and the second flexible layer and connected to the first flexible wiring.
In regards to claim 7, MUTO (Figs. 1-3 and associated text) discloses wherein the fixing structure (items FP1 or FP2) has a multi-layer structure of at least one of plastic, fiber, rubber, sponge, urethane, carbon material, ceramic, metal, and porous material.
In regards to claim 8, MUTO (Figs. 1-3 and associated text) discloses wherein the fixing structure is formed of a conductive material, wherein the semiconductor memory module (Figs. 1-3) further includes: a first conductive pattern disposed on the lower surface of the first substrate (item 21) and electrically connecting the fixing structure (items FP1 or FP2) and one of the first semiconductor packages (item 31); and a second conductive pattern disposed on the upper surface of the second substrate (item 22) and electrically connecting the fixing structure (items FP1 or FP2) and one of the second semiconductor packages (items 27, 28).
In regards to claim 10, MUTO (Figs. 1-3 and associated text) discloses wherein the fixing structure (items FP1 or FP2) includes: a first slot in which the first corner of the first substrate (item 21) is inserted; and a second slot in which the second corner of the second substrate (item 22) is inserted.
In regards to claim 11, MUTO (Figs. 1-3 and associated text) discloses wherein the first substrate (item 21) includes a first side recessed portion, wherein the second substrate (item 22) includes a second side recessed portion corresponding to the first side recessed portion, wherein the semiconductor memory module (Figs. 1-3) further includes a first capacitor (item 30) disposed in the first side recessed portion and connected to the first substrate (item 21), and wherein an upper surface of the first capacitor (item 30) is inserted in the second side recessed portion.
In regards to claim 12, MUTO (Figs. 1-3, 6 and associated text) discloses further comprising: a case (item 11) housing the first substrate (item 21), the first semiconductor packages (item 31), the second substrate (item 22), the second semiconductor packages (item 27, 28), and the fixing structure (items FP1, FP2); a first thermal interface material layer (item 32, 33) interposed between the first semiconductor packages (item 31) and the case (item 11); and a second thermal interface material layer (items 32, 33) interposed between the second semiconductor packages (item 27, 28) and the case (item 11).
In regards to claim 15, MUTO (Figs. 1-3, 6 and associated text) discloses further comprising: a frame (item 25) interposed between the first substrate (item 21) and the second substrate (item 22); and third semiconductor packages (item 31) mounted on an upper surface of the first substrate (item 21) and spaced apart from the frame.
In regards to claim 19, MUTO (Figs. 1-3, 6 and associated text) discloses a semiconductor memory module (Figs. 1-3) comprising: a first substrate (item 21) including a first corner and a first side surface; first semiconductor packages (item 31) mounted on a lower surface of the first substrate (item 21); a second substrate (item 22) disposed over the first substrate (item 21) and including a second corner and a second side surface respectively corresponding to the first corner and the first side surface; second semiconductor packages (items 27, 28) mounted on an upper surface of the second substrate (item 22); a fixing structure in which the first corner and the second corner are inserted, the fixing structure (corner structures of item 11, shown but not labeled) fixing a distance between the first substrate (item 21) and the second substrate (item 22); and at least one flexible connector (items FP1, FP2) connecting the first side surface and the second side surface.
In regards to claim 20, MUTO (Figs. 1-3, 6 and associated text) discloses wherein the first substrate (item 21) includes a first side recessed portion, wherein the second substrate (item 22) includes a second side recessed portion corresponding to the first side recessed portion, wherein the semiconductor memory module (Figs. 1-3) further includes a first capacitor (item 30) disposed in the first side recessed portion and connected to the first substrate (item 21), and wherein an upper surface of the first capacitor (item 30) is inserted in the second side recessed portion.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8, 9, 13, 14 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over MUTO (US 2021/0015006 A1).
In regards to claim 8, MUTO (Figs. 1-3 and associated text) does not specifically disclose further comprising: a third substrate disposed below the first substrate; third semiconductor packages mounted on a lower surface of the third substrate; and a second flexible connector connecting the third substrate and the first substrate, wherein the first substrate has a third side surface opposite to the first side surface, wherein the third substrate has a fourth side surface positioned below the third side surface, and wherein the second flexible connector connects the third side surface and the fourth side surface.
It would have been obvious to modify the invention to include a third substrate disposed below the first substrate; third semiconductor packages mounted on a lower surface of the third substrate; and a second flexible connector connecting the third substrate and the first substrate, wherein the first substrate has a third side surface opposite to the first side surface, wherein the third substrate has a fourth side surface positioned below the third side surface, and wherein the second flexible connector connects the third side surface and the fourth side surface, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193 USPQ 8).
In regards to claims 9 and 18, MUTO (Figs. 1-3 and associated text) disclose wherein the fixing structure (corner structure of item 11, shown but not labeled) has an ‘L’ shape, an ‘I’ shape, a triangle shape, or a quadrangular shape when viewed in a plan view.
It would have been obvious to modify the invention to include a fixing structure having an ‘L’ shape, an ‘I’ shape, a triangle shape, or a quadrangular shape when viewed in a plan view, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 13, MUTO (Figs. 1-3, 6 and associated text) discloses wherein a density of the first thermal interface material layer (items 32, 33) is different from a density of the second thermal interface material layer (items 32, 33).
In regards to claim 14, MUTO (Figs. 1-3, 6 and associated text) discloses wherein the thickness of the first thermal interface material layer(items 32, 33) is different from the thickness of the second thermal interface material layer (items 32, 33).
It would have been obvious to modify the invention to include a first thermal interface material layer being different from the thickness of the second thermal interface material layer, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 16, MUTO (Figs. 1-3, 6 and associated text) discloses a semiconductor memory module (Figs. 1-3, 6) comprising: a case (item 11); and a stacked structure (item 3) housed in the case (item 11), wherein the stacked structure includes: a first substrate (item 21) including a plurality of first corners and having a first side surface and a second side surface; first semiconductor packages (item 31) mounted on a lower surface of the first substrate (item 21); second semiconductor packages (item 31) mounted on an upper surface of the first substrate (item 21); a second substrate (item 22) disposed over the first substrate (item 21), the second substrate (item 22) including a plurality of second corners with each second corner respectively corresponding to a respective first corner, and the second substrate (item 22) having a third side surface and a fourth side surface; third semiconductor packages (item 27, 28) mounted on an upper surface of the second substrate (item 22); a plurality of fixing structures (corner structures of item 11, shown but not labeled) in which corresponding pairs of the first corners and the second corners are fitted in a respective fixing structure (corner structure of item 11, shown but not labeled) of the plurality of fixing structures (corner structures of item 11, shown but not labeled); a frame (item 25) interposed between the first substrate (item 21) and the second substrate (item 22); at least one flexible connector (items FP1, FP2) connecting the second side surface and the fourth side surface; and at least one capacitor (item 30) connected to the first side surface, wherein at least one fixing structure of the plurality of fixing structures (corner structures of item 11, shown but not labeled) includes: a first slot in which one of the first corners is fitted; and a second slot in which one of the second corners is fitted, but does not specifically disclose wherein a length, width, or height of each of the fixing structures (corner structures of item 11, shown but not labeled) is in a range from 0.1 mm to 200 mm, wherein the distance between the first slot and the second slot is in a range from 0.1 mm to 100 mm.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a length, width, or height of each of the fixing structures being in a range from 0.1 mm to 200 mm, wherein the distance between the first slot and the second slot being in a range from 0.1 mm to 100 mm, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)). Examiner notes that the Applicant has not given any criticality as to where these values and/or ranges yield an unexpected advantage and/or result.
In regards to claim 17, MUTO (Figs. 1-3, 6 and associated text) discloses wherein the first side surface and the second side surface are recessed toward a center of the first substrate (item 21), wherein the third side surface and the fourth side surface are recessed toward a center of the second substrate (item 22).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 September 24, 2026
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