Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Specie I: FIGS. 1A-1D (claims 1-11 and 15-20) in the reply filed on 05/26/2026 is acknowledged.
Claim Objections
Claim 10 objected to because of the following informalities: “wherein a side surface of the lower via plug is directly in contact with a side surface of the lower via plug”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-7, 10-11 and 16-17 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by KANAMORI (Pub. No.: US 2020/0203329).
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Re claim 1, KANAMORI, FIG. 4 teaches a semiconductor device comprising:
a substrate having a cell area (I) and a via area (III);
a plurality of transistors (120) and a plurality of interconnections (160/170/180) disposed over the substrate;
a lower insulating layer (190) over the substrate to cover the plurality of transistors and the plurality of interconnections in the cell area and the via area;
a conductive common source region (205L/268/left 280/left 180 = [CCSR]) over the lower insulating layer in the cell area;
a conductive support pattern [CSP] and a lower via plug [VP] disposed in the lower insulating layer in the via area (III), wherein the conductive support pattern and the lower via plug is directly in contact with each other;
a word line stack (231-239, [0050]) disposed over the conductive common source region in the cell area, wherein the word line stack includes a plurality of word lines;
a dielectric layer stack (285La/285Lb/285U) disposed over the conductive support pattern [CSP], the lower via plug [VP], and the lower insulating layer (190) in the via area;
a vertical channel pillar (CH1/CH2) penetrating the word line stack to be connected to the conductive common source region [CCSR] in the cell area;
an upper via plug (260/261) penetrating the dielectric layer stack to be in contact with the lower via plug in the via area,
wherein:
the conductive common source region [CCSR] and the conductive support pattern [CSP] are disposed at a same horizontal level.
Re claim 2, KANAMORI, FIG. 4 teaches the semiconductor device of claim 1, wherein the conductive common source region [CCSR] and the conductive support pattern [CSP] include a same material.
Re claim 4, KANAMORI, FIG. 4 teaches the semiconductor device of claim 1, wherein the conductive common source region [CCSR] and the conductive support pattern [CSP] have a same vertical thickness.
Re claim 6, KANAMORI, FIG. 4 teaches the semiconductor device of claim 5, wherein the lower via plug [VP] and the conductive support pattern [CSP] include different materials from each other.
Re claim 7, KANAMORI, FIG. 4 teaches the semiconductor device of claim 1, wherein:
the plurality of transistors (120) include a first transistor disposed in the cell area and a second transistor disposed in the via area,
the plurality of the interconnections include a first interconnection [FIC] disposed in the cell area and a second interconnection disposed in the via area,
wherein the second interconnection [SIC] is electrically connected to the lower via plug.
Re claim 10, KANAMORI, FIG. 4 teaches the semiconductor device of claim 1, wherein the conductive common source region [CCSR] has a plate shape in a top view.
Re claim 11, KANAMORI, FIG. 4 teaches the semiconductor device of claim 1, wherein the conductive support pattern [CSP] has a segment shape in a top view.
Re claim 16, KANAMORI, FIG. 4 teaches the semiconductor device of claim 15, wherein the end portions of the word lines (231-239) form a staircase in the extension area.
Re claim 17, KANAMORI, FIG. 4 teaches the semiconductor device of claim 15, further comprising:
a through via plug [TVP]connected to the conductive common source region in the extension area,
wherein the through via plug is not in contact with the word lines (231-239) of the word line stack.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over KANAMORI.
Re claim 3, KANAMORI differs from the invention by not showing wherein each of the conductive common source region and the conductive support pattern includes a polysilicon layer doped with N- type ions.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the above said teaching since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416.
Re claim 9, KANAMORI differs from the claim invention by not disclosing wherein a top surface of the conductive common source region in the cell area and a top surface of the lower insulating layer in the via area are co-planar.
However, Applicant has not disclosed that the ranges are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, It would have been obvious to one having ordinary skill in the art at the time the invention was made to include the above said teaching, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997).
Claim(s) 5, 8, 12, 15 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KANAMORI in view of KIM (Pub. No.: US 2022/0068903).
Re claim 18, KANAMORI, FIG. 4 teaches a semiconductor device comprising:
a logic device layer (S1); and
a memory device layer (CELL1/CELL2) vertically stacked over the logic device layer, wherein the logic device layer comprises:
a substrate (101) having a cell area and a via area;
a first transistor (left 120) and a first interconnection [FIC] disposed over the substrate in the cell area [CA];
a second transistor (right 120) and a second interconnection (170) disposed over the substrate in the via area [VA]; and
an insulating layer (190) over the substrate to cover the first and second transistors and the first and second interconnections in the cell area and the via area,
a common source region [CCSR] disposed over the insulating layer in the cell area; and
a lower via plug [VP] and a support pattern [CSP] disposed in the insulating layer in the via area, wherein a side surface of the lower via plug is directly in contact with a side surface of the lower via plug,
wherein the memory device layer comprises:
a word line stack (231-239) disposed over the common source region in the cell area;
a plurality of vertical channel pillars (CH1/CH2) penetrating the word line stack in a vertical direction to be commonly connected to the common source region in the cell area;
a dielectric layer stack (28aLb/285Lb/285U) over the lower via plug and the support pattern in the via area; and
an upper peripheral contact plug (261/260) vertically penetrating the dielectric layer stack to be connected to the lower via plug in the via area.
Re claim 19, KANAMORI, FIG. 4 teaches a semiconductor device comprising:
a substrate having a cell area (I), an extension area (II), and a via area (III);
a plurality of transistors (260) and a plurality of interconnections ([FIC]/[SIC]) disposed over the substrate;
an insulating layer (190) over the substrate to cover the plurality of transistors and the plurality of interconnections;
a common source region [CCSR] disposed over the insulating layer in the cell area and the extension area;
a support pattern [CSP] and a lower via plug [VP] disposed in the insulating layer in the via area;
a word line stack (231-239) including a plurality of word lines disposed over the common source region in the cell area and the extension area, wherein ends of the word lines form a staircase in the extension area;
a plurality of vertical channel pillars (CH1/CH2) vertically penetrating the word line stack to be connected to the common source region in the cell area;
a dielectric layer stack (28aLb/285Lb/285U) disposed over the insulating layer in the via area;
an upper via plug (261/260) vertically penetrating the dielectric layer stack to be in contact with the lower via plug,
KANAMORI fails to teach the limitation of claims 5, 8, 12 and 15; wherein top surfaces of the lower via plug and the support pattern are co-planar, wherein the lower via plug has a height greater than that of the support pattern (claim 18); and word line contact plugs electrically connected to the ends of the word lines of the word line stack in the extension area;
wherein a side surface of the support pattern and a side surface of the lower via plug are directly in contact with each other,
wherein top surfaces of the lower via plug, the support pattern, and the insulating layer are co-planar (claim 19).
KIM teaches wherein the lower via plug (26+24+22+781) has a greater vertical thickness than the conductive support pattern (16) (claim 5).
wherein top surfaces of the conductive support pattern (16, FIG. 6L, ¶ [0057]) and the lower via plug are co-planar (26+24+22+781) (claim 8).
wherein the conductive support pattern (16, FIG. 6L) includes two segments in a top view (claim 12).
an extension area (area occupied by staircases, FIG. 9B) between the cell area (middle region) and the via area (far right and left); and
a plurality of word line contact plugs (86) disposed in the extension area,
wherein: the word line contact plugs are connected to end portions of the word lines in the extension area (46),
the word line stack (46) and the conductive common source region (10) extend toward the via area,
the word line contact plugs (86) are not in contact with the conductive common source region (10) (claim 15).
wherein top surfaces of the lower via plug (26+24+22+781) and the support pattern (16) are co-planar, wherein the lower via plug has a height greater than that of the support pattern (claim 18); and word line contact plugs (86, FIG. 4A) electrically connected to the ends of the word lines of the word line stack (46) in the extension area;
wherein a side surface of the support pattern (16) and a side surface of the lower via plug (26+24+22+781) are directly in contact with each other (claim 18)
wherein top surfaces of the lower via plug (26+24+22+781), the support pattern (16), and the insulating layer (763, [0067]) are co-planar (claim 19).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the connectivity of the memory die and the logic die as taught by KIM, [0003]).
Re claim 20, KANAMORI, FIG. 4 teaches the semiconductor device of claim 19, wherein the lower via plug (26+24+22+781) has a height greater than that of the support pattern (16).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2894
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