DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/5/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 7/2/2026 is acknowledged.
Claims 11-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/2/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7 and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US 2020/0357785 A1, hereinafter “Lu”).
Regarding independent claim 1, Lu discloses a manufacturing method of a power module, comprising:
bonding a semiconductor device 101/104 (collectively 101 “RDL” and “104 “die”- ¶0030) to a lower substrate 109 (“carrier… substrate”- ¶0064) (see Fig. 10C);
disposing an upper bonding member 103c-1 (“conductive member”- ¶0081) on an upper portion (i.e., collectively the top surfaces of 101 and 104) of the semiconductor device 101/104 (see Fig. 10C);
contacting a probe device 201 (“probe card”- ¶0070) with the upper bonding member 103c-1 (see Fig. 10D);
electrically connecting the probe device 201 to a tester, since electrical tests are performed using probe device 201 which would inherently require electrically connecting probe device 201 to a tester (¶¶0081-0085) (see Fig. 10D);
detecting electrical characteristics of the semiconductor device using the tester (¶¶0081-0085) (see Fig. 10D); and
bonding an upper substrate 105 (“die”- ¶0019) to the semiconductor device 101/104 with the upper bonding member 103c-1 (see Fig. 10E).
Regarding claim 2, Lu discloses the manufacturing method further comprising:
performing a molding operation after bonding the upper substrate 105 to the semiconductor device 101/104 (¶0087) (see Fig. 10F).
Regarding claim 7, Lu discloses wherein the probe device 201 comprises a contact pin 201c (“probe card terminal”- ¶0073) that is electrically connected to the tester and configured to contact the upper bonding member 103c-1 (¶¶0082-0085) (see Fig. 10D), and
wherein contacting the probe device 201 with the upper bonding member 103c-1 comprises electrically connecting the contact pin 201c to the semiconductor device 101/104 through the upper bonding member 103c-1 (¶¶0082-0085) (see Fig. 10D).
Regarding claim 13, Lu discloses wherein detecting the electrical characteristics of the semiconductor device 101/104 comprises:
applying, by the tester, an electrical signal to the semiconductor device 101/104through the probe device 201, since an electrical signal would inherently be sent by the tester to perform the electrical tests (¶¶0081-0085) (see Fig. 10D).
Regarding independent claim 14, Lu discloses a test method of a power module, comprising:
preparing the power module that is a device under test for testing electrical characteristics thereof (¶¶0081-0085);
contacting a probe device 201 (“probe card”- ¶0070) with the power module (see Fig. 10D);
electrically connecting the probe device 201 with a tester, since electrical tests are performed using probe device 201 which would inherently require electrically connecting probe device 201 to a tester (¶¶0081-0085) (see Fig. 10D); and
applying, by the tester, an electrical signal to the power module, since an electrical signal would inherently be sent by the tester to perform the electrical tests (¶¶0081-0085) (see Fig. 10D),
wherein preparing the power module comprises:
providing the power module in a work-in-process state in which a semiconductor device 101/104 (collectively 101 “RDL” and “104 “die”- ¶0030) is bonded to a lower substrate 109 (“carrier… substrate”- ¶0064), and a bonding member 103c-1 (“conductive member”- ¶0081) is disposed on an upper portion (i.e., collectively the top surfaces of 101 and 104) of the semiconductor device 101/104 (see Fig. 10C), and
wherein contacting the probe device 201 with the power module comprises contacting the probe device 201 with the bonding member 103c-1 disposed on the upper portion of the semiconductor device 101/104 of the power module in the work-in-process state (¶¶0081-0085) (see Fig. 10D).
Regarding claim 15, Lu discloses wherein the probe device 201 comprises one or more contact pins 201c (“probe card terminal”- ¶0085), wherein a number of the one or more contact pins 201c corresponds to a number of one or more semiconductor devices 101/104 of the power module, the one or more semiconductor devices 101/104 including the semiconductor device 101/104, and wherein contacting the probe device 201 with the power module comprises contacting the one or more contact pins 201c with the bonding member 103c-1 (see Fig. 10D).
Regarding claim 16, Lu discloses wherein the bonding member 103c-1 comprises a material having an electrical conductivity (¶0045).
Allowable Subject Matter
Claims 3-6, 8-10 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art of record including Lu, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] manufacturing method… further comprising: bonding a signal lead to the semiconductor device, wherein bonding the signal lead to the semiconductor device is performed between detecting the electrical characteristics of the semiconductor device and bonding the upper substrate”.
Regarding claim 4 (which claims 5-6 depend from), the prior art of record including Lu, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein bonding the semiconductor device to the lower substrate comprises: disposing a lower bonding member between a lower surface of the semiconductor device and the lower substrate; and boding the semiconductor device to the lower substrate with the lower bonding member”.
Regarding claim 8 (which claim 9 depends from), the prior art of record including Lu, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the probe device further comprises a plate to which a plurality of contact pins are detachably coupled, the contact pin being one of the plurality of contact pins, and wherein bonding the semiconductor device to the lower substrate comprises bonding a plurality of semiconductor devices to the lower substrate, the semiconductor device being one of the plurality of semiconductor devices”.
Regarding claim 10, the prior art of record including Lu, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein disposing the upper bonding member on the upper portion of the semiconductor device comprises disposing a first upper bonding member on an upper surface of the semiconductor device, and wherein contacting the probe device with the upper bonding member comprises contacting the probe device with the first upper bonding member”.
Regarding claim 17, the prior art of record including Lu, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein a finished product of the power module includes the semiconductor device bonded between an upper substrate 105 and the lower substrate, and wherein the work-in-process state of the power module is before the upper substrate is bonded to an upper portion of the semiconductor device through the bonding member”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lin et al. (US 2024/0272200 A1), which discloses a method comprising connecting a probe device to a semiconductor device and performing an electrical test.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/Primary Examiner, Art Unit 2817
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