DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-18, 21 and 22, in the reply filed on August 17, 2026 is acknowledged. Claims 19 and 20 have been cancelled by the Applicant. Action on the merits is as follows:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-9, 12-18, 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (Xi) (US 2023/0335585 A1).
In regard to claim 1, Xie (paragraphs 49-79, Fig. 8, 9, 14 and associated text) discloses a semiconductor device (Fig. 14), comprising: a frontside (upper surface of item 1120) and a backside (lower surface of item 120) opposite the frontside (upper surface of item 1120); a plurality of gate structures (item 910) laterally disposed relative to one another across the semiconductor device (Fig. 14) defining a frontside (upper surface of item 1120)of the semiconductor device (Fig. 14) and a backside (lower surface of item 120) of the semiconductor device (Fig. 14) opposite the frontside (upper surface of item 1120); and a cross-coupled circuit including: a first cross-couple connection (Figs. 8, 9, 14, gate electrodes structures 910 of the upper left and lower right transistors are connected through on opening 410 are therefore cross-coupled) disposed on the frontside and connecting two of the plurality of gate structures; and a second cross-couple connection (item 1410) disposed on the backside and connecting two of the plurality of gate structures (item 910) on the backside, but does not specifically disclose a first cross-couple connection (Figs. 8, 9, 14, gate electrodes structures 910 of the upper left and lower right transistors are connected through on opening 410 are therefore cross-coupled) disposed on the frontside.
However, Xie (Fig. 25 and associated text) discloses a first cross-couple connection (2530) disposed on the frontside to couple two gates (item 910).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of the various embodiments of Xie for the purpose of an electrical (cross-coupled) connection. One of ordinary skill would recognize that frontside cross-couple connections (as shown in Fig. 25) and backside cross-coupled connections (as shown in Fig. 14) or “direct” cross-coupled connections through the bonding oxide element (item 14) are alternatives being possible to establishing cross-coupled connections.
In regard to claim 4, Xie (paragraphs 49-79, Fig. 8, 9, 14 and associated text) discloses wherein the second cross-couple connection (item 1410) comprises a conductive path that includes middle of line gate contacts (item 1410 establishes a conductive path between two gate structures; as item 1410 includes middle of line contact, being the vertical parts of item 1410 contacting the gate structure, the conductive path formed by item 1410 includes middle of the line gate contacts).
In regard to claim 5, Xie (paragraphs 49-79, Fig. 8, 9, 14 and associated text) discloses wherein the conductive path includes interconnects that connect the middle of line gate contacts to a metal line (item 1410 includes a laterally extending metal line and a vertical gate contact contacting the gate structure and a contact between this metal line and the vertical gate contact forms an interconnect).
In regard to claims 6 and 14, Xie (paragraphs 49-79, Fig. 8, 9, 14 and associated text) discloses wherein the metal line (metal line of item 1410) is disposed in an N-P region between active areas.
In regard to claims 7 and 15, Xie (paragraphs 49-79, Fig. 8, 9, 14 and associated text) discloses wherein the interconnects are disposed at a middle of line level (the interconnects between the lateral metal line (item 1410) and the vertical gate contacts of item 1410 are at the middle of the line level).
In regard to claims 8 and 16, Xie (paragraphs 49-79, Fig. 8, 9, 14 and associated text) discloses wherein the cross- coupled circuit (item 1410) is disposed within two contacted poly pitches (CPP).
In regard to claim 9, Xie (paragraphs 49-79, Fig. 8, 9, 13, 14 and associated text) discloses a semiconductor device (Fig. 14), comprising: a frontside (upper surface of item 1120) and a backside (lower surface of item 120) opposite the frontside (upper surface of item 1120); source/drain (S/D) regions (item 240) laterally disposed relative to one another across the semiconductor device; a plurality of gate structures (item 910) disposed between the S/D regions (item 240); sacrificial placeholders (item 210) associated with the S/D regions (item 240) and disposed toward the backside of the semiconductor device; a backside gate contact (item 1310) disposed between the sacrificial placeholders to connect one of the plurality of gate structures (item 910) from the backside of the semiconductor device; and a cross-coupled circuit including: a first cross-couple connection (Figs. 8, 9, 14, gate electrodes structures 910 of the upper left and lower right transistors are connected through on opening 410 are therefore cross-coupled) disposed on the frontside and connecting two of the plurality of gate structures (item 910); and a second cross-couple connection (item 1410) disposed on the backside and connecting two of the plurality of gate structures (item 910) through the backside gate contact (item 1310, 1440, 1310 plus 1410 or 1310 plus 1430), but does not specifically disclose a first cross-couple connection (Figs. 8, 9, 14, gate electrodes structures 910 of the upper left and lower right transistors are connected through on opening 410 are therefore cross-coupled) disposed on the frontside.
However, Xie (Fig. 25 and associated text) discloses a first cross-couple connection (2530) disposed on the frontside to couple two gates (item 910).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of the various embodiments of Xie for the purpose of an electrical (cross-coupled) connection. One of ordinary skill would recognize that frontside cross-couple connections (as shown in Fig. 25) and backside cross-coupled connections (as shown in Fig. 14) or “direct” cross-coupled connections through the bonding oxide element (item 14) are alternatives being possible to establishing cross-coupled connections.
In regard to claim 12, Xie (paragraphs 49-79, Fig. 8, 9, 13, 14 and associated text) discloses wherein the second cross-couple connection (item 1410) comprises a conductive path that includes two backside gate contacts (item 1310), the two backside gate contacts including the backside gate contact (item 1310).
In regard to claim 14, Xie (paragraphs 49-79, Fig. 8, 9, 13, 14 and associated text) discloses wherein the conductive path includes interconnects that connect the two backside gate contacts (item 1310) to a metal line (line of item 1410).
In regard to claim 17, Xie (paragraphs 49-79, Fig. 8, 9, 13, 14 and associated text) discloses wherein the sacrificial placeholders include caps (item 120).
In regard to claim 18, Xie (paragraphs 49-79, Fig. 8, 9, 13, 14 and associated text) discloses wherein the backside gate contact (item 1310, 1440, 1310 plus 1410 or 1310 plus 1430) includes a narrower portion between the sacrificial placeholders and a wider portion on the caps (item 120).
In regard to claim 21, Xie (paragraphs 49-79, Fig. 8, 9, 13, 14 and associated text) discloses an integrated circuit (Fig. 14), comprising: a frontside (upper surface of item 1120) and a backside (lower surface of item 120) opposite the frontside (upper surface of item 1120); source/drain regions (item 240) laterally disposed relative to one another across the semiconductor device; a plurality of gate structures (item 910) disposed between the source/drain regions (item 240); a backside gate contact (item 1310) connected to one of the plurality of gate structures (item 910) from the backside of the integrated circuit; and a cross-coupled circuit including: a first cross-couple connection (Figs. 8, 9, 14, gate electrodes structures 910 of the upper left and lower right transistors are connected through on opening 410 are therefore cross-coupled) disposed on the frontside and connecting two of the plurality of gate structures (item 910); and a second cross-couple connection (item 1410) disposed on the backside and connecting two of the plurality of gate structures (item 910) through the backside gate contact (item 1310, 1440, 1310 plus 1410 or 1310 plus 1430), wherein the cross-coupled circuit (item 1410) is disposed within two contacted poly pitches (CPP), but does not specifically disclose a first cross-couple connection (Figs. 8, 9, 14, gate electrodes structures 910 of the upper left and lower right transistors are connected through on opening 410 are therefore cross-coupled) disposed on the frontside.
However, Xie (Fig. 25 and associated text) discloses a first cross-couple connection (2530) disposed on the frontside to couple two gates (item 910).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of the various embodiments of Xie for the purpose of an electrical (cross-coupled) connection. One of ordinary skill would recognize that frontside cross-couple connections (as shown in Fig. 25) and backside cross-coupled connections (as shown in Fig. 14) or “direct” cross-coupled connections through the bonding oxide element (item 14) are alternatives being possible to establishing cross-coupled connections.
In regard to claim 22, Xie (paragraphs 49-79, Fig. 8, 9, 13, 14 and associated text) discloses further comprising a backside dielectric layer (item 120) disposed over a backside surface of one of the plurality of gate structures (item 910), wherein the backside gate contact (item 1310, 1440, 1310 plus 1410 or 1310 plus 1430) extends through the backside dielectric layer (item 120) to contact the backside surface.
Claim(s) 2, 3, 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (Xi) (US 2023/0335585 A1) in view of Vesterbacka “A Static CMOS Master-Slave Flip-Flop Experiment”.
In regard to claims 2 and 10, Xie (paragraphs 49-79, Fig. 8, 9, 14 and associated text) discloses wherein the cross-coupled circuit includes a multiplexer circuit (latch cross coupling connections, which are often present in circuit designs, paragraph 2, and multiplexers are typical applications for such latch circuits), and wherein the first cross-couple connection connects a gate of an n-type field effect transistor (NFET) (lower/upper left transistor) to a gate of a p-type field effect transistor (PFET) (lower/upper right transistor).
Vesterbacka (Section 2) discloses multiplexers with cross-coupled gates.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings Vesterbacka for the purpose of an electrical (cross-coupled) connection.
In regard to claims 3 and 11, Xie (paragraphs 49-79, Fig. 8, 9, 14 and associated text) as modified by Vesterbacka (Section 2) discloses wherein the cross-coupled circuit includes a multiplexer circuit (latch cross coupling connections, which are often present in circuit designs, paragraph 2, and multiplexers are typical applications for such latch circuits)s and wherein the second cross-couple connection (item 1410) connects a gate of an n-type field effect transistor (NFET) (lower/upper left transistor) to a gate of a p-type field effect transistor (PFET) (lower/upper right transistor).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 September 15, 2026
Prosecution Insights