DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 2, 2026, and March 19, 2026 were considered by the examiner.
Election/Restrictions
Newly submitted claim 2 is directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Regarding claim 2,
Applicant has amended claim 1 to state that “a plurality of lithographically formed crude interconnections formed directly on the destination substate”. This means that per Applicant’s figure 19H, and based on the specification, the crude interconnect 1920 is formed on the destination substrate 1922. Because of this “each of the lithographically formed crude interconnections extends over an edge of and onto the intermediate substrate” of claim 2 cannot read on the elected species. Because as shown in figure 19H the crude interconnections 1920 do not extend onto the intermediate substrate 1902. Therefore, claim 2 is withdrawn from consideration.
Regarding claim 3,
Claim 3 requires “wherein each of the plurality of lithographically formed crude interconnections is directly electrically connected to one or more of the plurality of lithographically formed fine interconnections” This is not part of the elected species as shown in figure 19H. This is because the crude interconnections 1920 (as required to be from claim 1) are not directed connected to the fine interconnections 1912. Rather they are connected together by means of 1908. Therefore, claim 3 is withdrawn from consideration.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 2 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Continuation-in-part
Applicant states that this application is a continuation or divisional application of the prior-filed application. A continuation or divisional application cannot include new matter. Applicant is required to delete the benefit claim or change the relationship (continuation or divisional application) to continuation-in-part because this application contains the following matter not disclosed in the prior-filed application: Figure 19H.
Discussion of Figure 19H
History of Figure 19H
In the parent application, 14/822,868 on February 7, 2022 Applicant filed figure 20 (pictured below). It should be noted that this figure 20 was the last figure 20. The specification referenced below dates to August 24, 2018 which the below figure 20, and previous figure 20(s) relied on. Therefore, the specification dated August 24, 2018 which references figure 20 is all at issue in the discussion below.
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In the parent application on April 15, 2022 Examiner issued an Ex Parte Quayle action. On page 3 of this action Examiner stated the above figure 20 contained new matter, and was disapproved. Figure 20 was not entered.
In the parent application on June 15, 2022, Applicant filed a petition with the Director asserting the above figure 20 was not new matter and was supported by the specification and other figures.
In the parent application on March 28, 2023 the application went abandoned, and was revived on April 11, 202.
In the parent application on April 11, 2023, the June 15, 2022 petition decision was filed. In the petition decision the Director concluded 1) that figure 20 was new matter, pg. 4, 2) that no single embodiment showed every feature of the claim, and 3) the specification contained new matter.
In the parent application on April 11, 2023, Applicant filed a petition for revival. Applicant also filed a new figure 20, and amendments to the specification.
In the parent application on May 30, 2023, the petition to revive was granted.
In the parent application on June 27, 2023, Examiner issued an election of species.
In the parent application on October 23, 2023, Applicant elected Species B, figures 16A-16B, with traverse.
In the parent application on November 3, 2023, Examiner issued a non-responsive. Examiner responded to Applicant’s traversal, and issued another drawing objection.
In the parent application on February 5, 2024, Applicant bought a two-month extension of the parent application.
In the child application (current application) on February 5, 2024, Applicant filed the child application as a continuation application. This child application contains figure 19H (pictured below). As can be seen the only difference between figure 19H and figure 20 is that Applicant relabeled elements 1708a and 1708b in the parent application to 1920 in the child application.
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In the parent application on June 5, 2024, the parent application when abandoned.
In the child application on January 13, 2025, Examiner issued a restriction/election requirement.
In the child application on July 9, 2025, Applicant elected Species A7 and B4, figures 15A-B and 19A-H with traverse.
In the child application on July 24, 2025, Examiner issued a non-final office action. In this office action Examiner stated that figure 19H was not part of the parent application, new matter, and will not get the filing date of the parent application. Examiner stated that figure 19H will get the filing date of the child application February 5, 2024. Examiner also stated the specification in regards to figure 19H was also getting a filing date of the child application, February 5, 2024.
Applicant’s reply to Figure 19H dated January 26, 2026 (“Remarks”)
Applicant asserts that figure 19H is supported by the parent application. Remarks at pg. 8. In footnote 3, Applicant states figure 19H is supported by numerous arguments in the parent application. And, in footnote 4, Applicant again states that Figure 19H is supported by the parent application. Applicant also contends that priority is for a Court to determine not an Examiner. Remarks at page 8. Applicant in the Remarks at pages 8-9 also makes the same argument for the specification sections directed to Figure 19H.
Examiner response to Remarks, and Figure 19H determination
MPEP 201.07 states:
A continuation application is an application for the invention(s) disclosed in a prior- filed copending nonprovisional application, international application designating the United States, or international design application designating the United States. The disclosure presented in the continuation must not include any subject matter which would constitute new matter if submitted as an amendment to the parent application.
(emphasis added).
Figure 19H of the child application is the same subject matter which was determined by the Director to be new matter in the parent application in the petition decision issued on April 11, 2023. Therefore, Figure 19H is not considered part of the parent application for purposes of determining priority date in the child application. Thus, any claimed subject matter which requires the structure shown in Figure 19H shall have a priority date of consistent with the child applications filing date. This date shall be February 5, 2024.
Further, because figure 20 is not part of the drawings or specification in the parent application, and because the parent application was laid-open, or made of public record, as of the date of publication, March 31, 2016, and because figure 20 in the parent application was made public on February 7, 2022, it renders figure 20 in the parent application as prior art under 35 USC § 102(a)(1).
Further, figure 20 cannot be excluded as prior art under 102(b)(1)(A) or (B) as the grace period of 1 year only extends to February 5, 2023. In-line with this decision, the specification of the parent application which references figure 20 will also be treated as prior art for the same reason figure 20 is treated as prior art. Also, in-line with this decision in the child application (current application) all reference to figure 20 and its corresponding specification section will be deemed to be filed on February 5, 2023, and all claims directed to figure 20 and its corresponding specification section will have a filing date of February 5, 2023.
Filing date of the claims
Claim 1 reads, and requires, the structure shown in figure 19H. Based upon the section Discussion of Figure 19H above, claim 1, and all claims which depend upon it are deemed to have a filing date of February 5, 2023.
Consistent with the Discussion of Figure 19H above, figure 19H from the parent application, and its corresponding specification section, are deemed prior art under 35 USC § 102(a)(1), and there is no 35 USC § 102(b)(1)(A) or (B) exception applicable.
Claim Rejections - 35 USC § 112(b)
Examiner withdraws the 35 USC § 112(b) rejection based upon the cancelation of claims 12-13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 8-11, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over X-Celeprint figure 20 from the parent application (as explained in the Discussion of Figure 19H section above) (“X-Celeprint”), in view of Sadamasa et al. (US 4,322,735) (“Sadamasa”).
Regarding claim 1, X-Celeprint teaches in figure 20:
a destination substrate (1740);
one or more micro-systems (detailed below; hereinafter “A”) printed on (this is a product-by-process limitation. The end result is a micro-system on the destination substrate) and non-native to the destination substrate (1704),
wherein each of the one or more micro-systems (A, which is described below) comprises:
(i) an intermediate substrate (1902),
(ii) a plurality micro-devices (1910a-b) printed on (this is a product-by-process limitation) and non-native to the intermediate substrate (1902), and
(iii) a lithographically (this is a product-by-process limitation) formed fine interconnections (1912),
wherein,
the lithographically formed fine interconnections (1912) comprises at least a portion (a portion of 1912) formed exclusively and directly on the intermediate substrate (1902).
each of the plurality of lithographically formed fine interconnections (1912) has a fine interconnection width greater than or equal to 100 nm and less than 10 µm (1912; Specification dated, and publicly available, August 24, 2018, referenced figure 20 as a fine conductive line on pg. 32 at line 25, which is disclosed as being 100nm to 10 µm on pg. 30 at lines 23-24), and
the lithographically formed fine interconnections (1912) is electrically connected to at least one of the plurality of microdevices (1910a-b), and
the micro-devices (1910a-b) disposed on the intermediate substrate (1902) are electrically connected using the fine interconnections (pg. 32 at lines 21-24, where the process to make figure 19H is disclosed and informs on figure 19H); and
a lithographically (this is a product-by-process) formed crude interconnections (1920) formed directly on the destination substrate (1922),
wherein the crude interconnections (1708a-b) are electrically connected to the fine interconnections (1912) of the micro-systems (A) and
each of the crude interconnections (1708a-b) has a width greater than or equal to 10 µm and less than or equal to 2 mm (pg. 32 at lines 1-2, where 1708a-b are referred to as crude lithography)
X-Celeprint does not teach:
(iii) a plurality of lithographically (this is a product-by-process limitation) formed fine interconnections,
each of the plurality of lithographically formed fine interconnections comprises at least a portion formed exclusively and directly on the intermediate substrate.
a min spacing equal to or greater than the fine interconnection width.
each of the plurality of lithographically formed fine interconnections is electrically connected to at least one of the plurality of microdevices.
the plurality of micro-devices printed (product-by-process) on the intermediate substrate are electrically connected only using the plurality of lithographically formed fine interconnects
a plurality of lithographically (this is a product-by-process) formed crude interconnections formed directly on the destination substrate,
wherein each of the plurality of lithographically formed crude interconnections are electrically connected to at least one of the plurality of lithographically formed fine interconnections of the micro-systems and
This is because X-Celeprint teaches:
A selected cross-sectional area of the device. What X-Celeprint is not teaching is the plurality of interconnections.
Sadamasa teaches at least in figure 3:
(iii) a plurality of lithographically (this is a product-by-process limitation) formed fine interconnections (14/38; where the wire 38 performs the same function as X-Celeprint 1908, which is to make an electrical connection from the micro-devices to the outside world.),
each of the plurality of lithographically formed (this is a product-by-process limitation) fine interconnections (38) is electrically connected to at least one of the plurality of microdevices (37a-d).
the plurality of micro-devices (37a-d) printed (product-by-process) on the intermediate substrate (33/34) are electrically connected only using the plurality of lithographically formed (product-by-process) fine interconnects (figure 1 showing how the devices are electrically connected to together using wires 14)
a plurality of lithographically (this is a product-by-process) formed crude interconnections (12/47) formed directly on the destination substrate (31/32),
wherein each of the plurality of lithographically formed (this is a product-by-process) crude interconnections (31/32) are electrically connected to at least one of the plurality of lithographically formed (this is a product-by-process) fine interconnections (14/38) of the micro-systems (A).
It would have been obvious to one of ordinary skill in the art before the filing date of February 5, 2024 to combine Sadamasa and X-Celeprint. As shown the combination of Sadamasa and X-Celeprint is teaching that X-Celeprint can have a plurality of the claimed elements. It would have been obvious that one could have made X-Celeprint to have a plurality of wiring to connect the plurality of micro-devices because it would have been obvious that one would need a plurality of wiring to connect said micro-devices or else the micro-devices are taking up room and very expensive real estate without performing a function.
The combination of Sadamasa and X-Celeprint teach:
each of the plurality of lithographically formed fine interconnections (X-Celeprint 1912; Sadamasa 38) comprises at least a portion (X-Celeprint a portion of 1912) formed exclusively and directly on the intermediate substrate (X-Celeprint 1902).
The combination of Sadamasa and X-Celeprint do not teach:
a min spacing equal to or greater than the fine interconnection width.
However, this would have been obvious to one of ordinary skill in the art based upon the design requirements of the technology node they are designing for. There are industry standard minimum requirement spacing for interconnection wires. The terms fine and crude simply denote a size. One of ordinary skill in the art would know the pros and cons of the minimum spacing requirements. Some of the design considerations are capacitance, signal interference, accidently creating an antenna, closeness to power and ground, whether the fine interconnections need to be differential pairs, etc. Thus, while not taught directly by Sadamasa or X-Celeprint this is a well-known aspect of device design known, and routinely performed, by those of ordinary skill in the art.
Regarding claim 6, Sadamasa teaches at least in figure 3-4:
wherein the micro-devices comprise a first micro-device comprising a first semiconductor material and a second micro-device comprising a second semiconductor material and the first semiconductor material is a different semiconductor from the second semiconductor material (col. 4 at lines 43-46, where different color LEDs have different semiconductor material).
Regarding claim 8, Sadamasa teaches at least in figure 3-4:
wherein the micro-systems are pixels (the LEDs can be considered pixels).
Regarding claim 9, Sadamasa teaches at least in figure 3-4:
wherein the macro-system is a heterogeneously integrated system (the device of claim 1 is so integrated).
Regarding claim 10, Sadamasa teaches at least in figure 3-4:
wherein the micro-devices (col. 4 at lines 43-46) and the destination substrate are made of different materials (col. 2 at lines 65-68).
Regarding claim 11, the combination of X-Celeprint and Sadamasa teach:
Wherein each of the one or more micro-systems (A) comprises (detailed below)
A plurality of connection pads (X-Celeprint 1908; the plurality is taught be Sadamasa see claim 1),
Wherein the plurality of lithographically formed (product-by-process) fine interconnections (X-Celeprint 1912; the plurality is taught be Sadamasa see claim 1) are electrically connected to the plurality of lithographically formed (product-by-process) crude interconnections (X-Celeprint 1708a-b; the plurality is taught be Sadamasa see claim 1).
Regarding claim 15,
The entire device can be considered an integrated circuit.
Regarding claim 16, Sadamasa teaches at least in figure 3-4:
wherein the destination substrate (31/32) has a contiguous substrate area (it is so),
the micro devices (37a-c and/or 44a-c) each have a device area (they so have an area) and are each disposed within the contiguous substrate area (they are so disposed), and
the device area of the micro devices of all of the micro-systems combined is less than or equal to one-quarter of the contiguous substrate area (Under MPEP 2144.04(IV)(A) this is considered a change in size/proportion of the micro devices as relatively compared to the destination substrate. There is no evidence the claimed dimension would perform differently than the prior art device, and thus is not patentably distinct).
Regarding claim 17, Sadamasa teaches at least in figure 3-4:
where the plurality of micro devices (37a-c and/or 44a-c) are distributed over the contiguous substrate area (31/32) in an array (figure 4).
Regarding claims 18-20, Sadamasa teaches at least in figure 3-4:
The device of claim 1 can be considered multi-functional, polyfunctional, and/or a display.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over X-Celeprint, in view of Sadamasa, in view of Vaassen et al. (US 2010/0060205 A1) (“Vaassen”), in view of official notice.
Regarding claim 7, Sadamasa teaches at least in figure 3-4:
wherein the first micro-device is a light emitting diode (37a-b),
the first semiconductor material is a compound semiconductor (col. 4 at lines 43-46).
Sadamasa does not teach:
the second micro-device is a control circuit, and
the second semiconductor material is silicon.
Vassen teaches at least in figure 3:
the second micro-device is a control circuit (CNTL).
It would have been obvious to one of ordinary skill in the art to add a control circuit to the device of Sadamasa to provide different control functions to the LEDs. These control functions can be to turn on or off, for example.
In regards to the limitation the second semiconductor material is silicon,
Examiner is taking official notice that semiconductor devices which can function as a control chip can be made out of silicon. A classic example is the 8086 microprocessor.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sadamasa, in view of Ishikawa et al. (US 2011/0067911 A1) (“Ishikawa”)
Regarding claim 14, Sadamasa does not teach:
wherein each of the micro-devices has at least one dimension from 2 to less than 20 µm.
Ishikawa teaches
wherein each of the micro-devices has at least one dimension from 2 to less than 20 µm (¶ 0052).
It would have been obvious to one of ordinary skill in the art to combine the prior references with Ishikawa because Ishikawa teaches possible dimensions than an LED may have. Additionally, one of ordinary skill in the art would know the size of the LEDS is a result dependent variable proportional to the light emitted, current needed, amount of heat dissipation during use, etc. Therefore, it would be a matter of optimizing the size of the LED for the intended use of said LED.
Claim Interpretation
Applicant’s arguments with respect to the rejection(s) of claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the prior art as discussed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VINCENT WALL/ Primary Examiner, Art Unit 2898
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