DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-3, 5, 14, 18, 20, and 22 are amended. Claim 24 is new, no new matter is present. Claims 1-24 are present for examination.
Response to Arguments
Applicant’s arguments, see page 10, filed July 29, 2026, with respect to the title objection have been fully considered and are persuasive. The title objection of March 31, 2026 has been withdrawn.
Applicant’s arguments, see pages 10-11, filed July 29, 2026, with respect to the rejection(s) of claim 14 under 35 U.S.C. 112 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chen (US 2022/0384677 A1).
Applicant’s arguments, see pages 12-19, filed July 29, 2026, with respect to the rejection(s) of claims 1-23 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ogawa (US 2023/0025876 A1).
In the interest of compact prosecution, the Examiner suggests the Applicant more clearly define the direct contact made between the adhesive layer and the first semiconductor layer of the micro light emitting diode, as well as the under-lying display panel (e.g. wherein the adhesive layer is in direct vertical contact with the display panel and micro light emitting diode, wherein a bottom surface of the first semiconductor layer is in direct contact with the adhesive layer and includes a plurality of convex portions and a plurality of concave portions). The Examiner is available at the number below for an interview to discuss ideas at the Applicant’s convenience.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7-9, 11-12, and 15-24 are rejected under 35 U.S.C. 103 as being unpatentable over An (US 2021/0328107 A1) in view of Lee (US 2022/0302203 A1), and further in view of Ogawa (US 2023/0025876 A1).
Claim 1, An discloses a display device (light emitting display device, [0080], Fig. 1), comprising:
a display panel (display area DA is a display panel, hereinafter, display panel DA, [0081], Fig. 1) including a plurality of subpixels (display panel DA includes a plurality of pixels, [0082], Fig. 1);
a light emitting diode (light emitting diode LED, [0096], Fig. 3) in a subpixel (each subpixel includes an light emitting diode LED (i.e. each subpixel includes a unique color filter layer 230R/230G/230B, hereinafter, subpixel 230R/230G/230B), [0096], Fig. 3) from the plurality of subpixels 230R/230G/230B (each light emitting diode LED is in a subpixel from the plurality of subpixels 230R/230G/230B (i.e. plurality of subpixels includes each subpixel 230R/230G/230B), [0096], Fig. 3);
a first planarization layer (partition wall 370 is a first planarization layer, hereinafter, first planarization layer 370, [0096], Fig. 3) that encloses the light emitting diode LED (first planarization layer 370 encloses the light emitting diode LED, [0096], Fig. 3); and
a connection electrode (Lee, first connection electrode CNE1, [0178], Figs. 6-7; An, common electrode 270 is a connection electrode, hereinafter, connection electrode 270, [0109], Fig. 3) on the second planarization layer (Lee, first connection electrode CNE1 is on the second planarization layer PAS3, [0178], Figs. 6-7; An, connection electrode 270 is on the first planarization layer 370, [0096], Annotated Fig. 3), the connection electrode connected to the light emitting diode (Lee, first connection electrode CNE1 is connected to the light emitting diode 30, [0147], Figs. 6-7; An, connection electrode 270 is connected to the light emitting diode LED, [0109], Fig. 3),
wherein the first planarization layer (An, first planarization layer 370, [0096], Annotated Fig. 3; Lee, first planarization layer PAS3, [0178], Fig. 6) includes a first open area that encloses the light emitting diode (Lee, first open area (i.e. opening OP) that encloses the light emitting diode 30, [0161], Fig. 6; An, first planarization layer 370 includes a first open area (i.e. pixel opening 351) that encloses the light emitting diode LED, [0096], Annotated Fig. 3 and Fig. 12) and a portion of the first planarization layer corresponding to the first open area has a first thickness that is less than a second thickness of a second portion of the first planarization layer (An; first portion of the first planarization layer 370 corresponding to the first open 351 area (i.e. near LED) has a first thickness that is less than a thickness of the second portion of the first planarization layer 370, [0096], Annotated Fig. 3; Lee, first planarization layer PAS3).
An does not explicitly disclose a second planarization layer on the first planarization layer and the light emitting diode.
However, Lee disclose a second planarization layer (Lee, third insulating layer PAS3 is a second planarization layer, hereinafter, second planarization layer PAS3, [0178], Fig. 6; An, first planarization layer 370, [0096], Annotated Fig. 3) that is on the light emitting diode (Lee, second planarization layer PAS3 is on the light emitting diode 30, [0178], Fig. 6; An, first planarization layer 370, [0096], Annotated Fig. 3) and the first planarization layer (Lee, second planarization layer PAS3 is on the first planarization layer PAS1, [0178], Fig. 6; An, first planarization layer 370, [0096], Annotated Fig. 3). The combination to utilize an additional planarization layers near the light emitting diode allows for a resultant display device capable of preventing a short circuit or burning between wires and reducing static electricity or noise signals that may be applied externally (Lee, [0201]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an additional planarization layers near the light emitting diode to allow for a resultant display device capable of preventing a short circuit or burning between wires and reducing static electricity or noise signals that may be applied externally (Lee, [0201]).
An/Lee does not explicitly disclose a display panel including a plurality of pixels, each of the plurality of pixels including a plurality of subpixels;
A micro light emitting diode in a subpixel from the plurality of subpixels, and
Wherein the plurality of subpixels of one pixel from the plurality of pixels includes at least two subpixels configured to emit different colors from each other, and at least two subpixels configured to emit a same color as each other.
However, Ogawa (US 2023/0025876 A1) discloses a display panel (Ogawa, display device DSP is a display panel, hereinafter, display panel DSP, [0024], Fig. 1) including a plurality of pixels, each of the plurality of pixels including a plurality of subpixels (Ogawa, display panel DSP includes a plurality of pixels PX/PX/PX, each of the plurality of pixels PX/PX/PX includes a plurality of subpixels, hereinafter, plurality of subpixels SPa/SPb/SPc, [0024], Fig. 1; An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1);
a micro light emitting diode in a subpixel from the plurality of subpixels (Ogawa, micro light emitting diode 10 is in a subpixel SP from the plurality of subpixels SPa/SPb/SPc, [0024], Fig. 1; An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1), and
wherein the plurality of subpixels of one pixel from the plurality of pixels includes at least two subpixels configured to emit different colors from each other (Ogawa, the plurality of subpixels SPa/SPb/SPc of one pixel PX from the plurality of pixels PX/PX/PX includes at least two subpixels configured to emit different colors from each other (i.e. each group of subpixels within a pixel includes a red, green, and blue micro LED), [0024], Fig. 1; An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1), and at least two subpixels configured to emit a same color as each other (Ogawa, the plurality of subpixels SPa/SPb/SPc of one pixel PX from the plurality of pixels PX/PX/PX includes at least two subpixels configured to emit a same color as each other (i.e. each group of subpixels PX within a pixel includes a red, green, and blue micro LED and may emit a same color as the adjacent group of subpixels PX), [0024], Fig. 1; An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1). The combination to utilize micro light emitting diodes in combination with a plurality of adjacent subpixels ensures a resultant display device capable of improving the front luminance (Ogawa, [0134]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize micro light emitting diodes in combination with a plurality of adjacent subpixels ensures a resultant display device capable of improving the front luminance (Ogawa, [0134]).
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Annotated Fig. 13 (Ogawa) - Illustrates a plurality of pixels PX/PX/PX, wherein each of the each of the plurality of pixels PX/PX/PX includes a plurality of subpixels SPa/SPb/SPc within each group of subpixels PX
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Annotated Fig. 3 (An) - Illustrates a first planarization layer 370 including a first portion that is in direct contact with a portion of a side surface of the light emitting diode LED and a second portion that extends from the first portion.
Claim 2, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 1.
An/Lee/Ogawa discloses wherein the first open area overlaps the light emitting diode in a plan view of the display device (Lee, first open area OP overlaps the light emitting diode 30 in a plan view of the display device, [0161], Fig. 6; An, first open area pixel opening 351 overlaps the light emitting diode LED in a plan view of the display device, [0096], Annotated Fig. 3 and Fig. 12; Ogawa, display panel DSP, [0024], Fig. 1) and the first open area has an area that is larger than an area of the light emitting diode (Lee, first open area OP has an area that is larger than an area of the light emitting diode 30, [0161], Fig. 6; An, first open area pixel opening 351 has an area that is larger than an area of the light emitting diode LED, [0096], Annotated Fig. 3 and Fig. 12; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 3, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 2.
An/Lee/Ogawa discloses wherein the first planarization layer (An, first planarization layer 370, [0096], Annotated Fig. 3; Lee, first planarization layer PAS3, [0178], Fig. 6; Ogawa, display panel DSP, [0024], Fig. 1) is in direct contact with a side surface of the light emitting diode in the first open area (An, first planarization layer 370 is in direct contact with a side surface of the light emitting diode LED in the first open area 351, [0096], Annotated Fig. 3; Lee, first planarization layer PAS2/PAS3 (i.e. first planarization layer PAS3 includes second insulating layer PAS2, hereinafter, first planarization layer PAS2/PAS3) is in direct contact with a side surface of the light emitting diode 30 between the first open areas OP, [0178], Fig. 6; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 5, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 1.
An/Lee/Ogawa discloses wherein the light emitting diode (An, light emitting diode LED, [0096], Fig. 3; Lee, light emitting element 30, [0084], Fig. 6; Ogawa, display panel DSP, [0024], Fig. 1) includes:
a first semiconductor layer (Lee, first semiconductor layer 31, [0185], Fig. 7; An, pixel electrode 191 includes a metal layer (i.e. first electrode) disposed on a transparent conductive oxide film which is a first semiconductor layer, hereinafter, first semiconductor layer 191_S, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) on the display panel (Lee, first semiconductor layer 31 is on the display panel, [0185], Fig. 7; An, first semiconductor layer 191_S is on the display panel, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1);
a second semiconductor layer (Lee, second semiconductor layer 32, [0186], Fig. 7; An, first semiconductor layer 191_S, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) on the first semiconductor layer (Lee, second semiconductor layer 32 is on the first semiconductor layer 31, [0186], Fig. 7; An, first semiconductor layer 191_S, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1);
an emission layer (Lee, light emitting layer 36 is an emission layer, hereinafter, emission layer 36, [0186], Fig. 7; An, emission layer 350, [0108], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) between the first semiconductor layer and the second semiconductor layer (Lee, emission layer 36 is between the first semiconductor layer 31 and the second semiconductor layer 32, [0186], Fig. 7; An, emission layer 350 is on the first semiconductor layer 191_S, [0108], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1);
a first electrode (Lee, connection electrode CNE2 is a first electrode, hereinafter, first electrode CNE2, [0147], Fig. 7; An, pixel electrode 191 includes a metal layer which is a first electrode, hereinafter, first electrode 191_M, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) on the first semiconductor layer (Lee, first electrode CNE2 is on the first semiconductor layer 31, [0147], Figs. 6-7; An, first electrode 191_M is on the first semiconductor layer 191_S, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) and is spaced apart from the emission layer (Lee, first electrode CNE2 is spaced apart from the emission layer 36, [0186], Figs. 6-7; An, first electrode 191_M is spaced apart from the emission layer 350, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1);
a second electrode (Lee, electrode layer 37 is a second electrode, hereinafter, second electrode 37, [0170], Figs. 6-7; An, common electrode 270 is a second electrode, hereinafter, second electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) on the second semiconductor layer (Lee, second electrode 37 is on the second semiconductor layer 32, [0170], Figs. 6-7; An, second electrode 270 is on the first semiconductor layer 191_S and would include a second semiconductor layer if second electrode 270 utilized a similar multilayer structure as utilized by the first electrode 191_M, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1); and
an encapsulation layer (Lee, fourth insulating layer PAS4 is an encapsulation layer, hereinafter, encapsulation layer PAS4, [0179], Fig. 6; An, encapsulation layer 400, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) that encloses a first part of a side surface of the first semiconductor layer (Lee, encapsulation layer PAS4 encloses the entirety of the first semiconductor layer 31, [0179], Fig. 6; An, encapsulation layer 400 encloses the entirety of the first semiconductor layer 191_S, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1), the emission layer (Lee, encapsulation layer PAS4 encloses the emission layer 36, [0186], Fig. 7; An, encapsulation layer 400 encloses the emission layer 350, [0108], Fig. 3), the second semiconductor layer (Lee, encapsulation layer PAS4 encloses the second semiconductor layer 32, [0186], Fig. 7; An, encapsulation layer 400, [0108], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1), the first electrode (Lee, encapsulation layer PAS4 encloses the first electrode 191_M, [0186], Fig. 7; An, encapsulation layer 400 encloses the first electrode 191_M, [0108], Fig. 3), and the second electrode (Lee, encapsulation layer PAS4 encloses second electrode 37, [0170], Figs. 6-7; An, encapsulation layer 400 encloses the second electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 7, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 1.
An/Lee/Ogawa discloses wherein the first planarization layer (An, first planarization layer 370, [0096], Annotated Fig. 3; Lee, first planarization layer PAS3, [0178], Fig. 6; Ogawa, display panel DSP, [0024], Fig. 1) further includes a second open area through an entire thickness of the first planarization layer (Lee, first and second open area (i.e. opening OP) that encloses the light emitting diode 30, wherein second open area OP is through an entire thickness of the first planarization layer PAS3, [0161], Fig. 6; An, first planarization layer 370 includes a first open area (i.e. pixel opening 351), and the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) further comprising:
a reflection plate (Lee, electrodes 21 and 22 function as a reflection plate, hereinafter, reflection plate 21/22, [0149], Fig. 6; An, Annotated Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) connected to a pixel circuit of the display panel (Lee, reflection plate 21/22 is connected to a pixel circuit (i.e. first transistor T1, [0083]) of the display panel, [0149], Fig. 6; An, Annotated Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1), the reflection plate in contact with the connection electrode (Lee, reflection plate 21/22 is in contact with the first connection electrode CNE1, [0178], Figs. 6-7; An, connection electrode 270, [0109], Fig. 3) through the second open area (Lee, reflection plate 21/22 is in contact with the first connection electrode CNE1 through the second open area OP, [0178], Figs. 6-7; An, connection electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 8, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 5.
An/Lee/Ogawa discloses wherein the second planarization layer (Lee, second planarization layer PAS3, [0178], Fig. 6; An, first planarization layer 370, [0096], Annotated Fig. 3) includes a plurality of third open areas over the first electrode (Lee, there are a plurality of third open areas OP over first electrode CNE2, [0147], Fig. 7; An, first electrode 191_M, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) and the second electrode (Lee, there are a plurality of third open areas OP over second electrode 37, [0170], Figs. 6-7; An, second electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1), and the connection electrode (Lee, first connection electrode CNE1, [0178], Figs. 6-7; An, connection electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) is in contact with at least one of the first electrode or the second electrode in the plurality of third open areas (Lee, connection electrode CNE1 is in contact with at least one of the first electrode CNE2 in the plurality of third open areas OP, [0178], Figs. 6-7; An, connection electrode 270 is in contact with at least one of the first electrode 191_M in the plurality of third open areas 351, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 9, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 8.
An/Lee/Ogawa discloses wherein the plurality of third open areas are in the first open area (Lee, plurality of third open areas OP are in the first open area OP, [0170], Figs. 6-7; An, Fig. 3), and the connection electrode (Lee, connection electrode CNE1, [0178], Figs. 6-7; An, connection electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) is in direct contact with the first planarization layer in the plurality of third open areas (Lee, connection electrode CNE1 is in direct contact with the first planarization layer PAS3 in the plurality of third open areas OP, [0178], Figs. 6-7; An, connection electrode 270 is in direct contact with the first planarization layer 370 in the plurality of third open areas 351, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 11, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 8.
An/Lee/Ogawa discloses wherein a long axis direction of the plurality of third open areas is in a first direction (Lee, long axis direction of the plurality of third open areas OP is in a first direction (i.e. DR3), [0170], Figs. 6-7; An, first electrode 191_M and second electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) and a long axis direction of the first electrode and the second electrode (Lee, long axis direction of the first electrode CNE2 and the second electrode 37 (i.e. DR1), [0170], Figs. 6-7; An, second electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) is in a second direction that is different from the first direction (Lee, second direction DR1 is different than the first direction DR3, [0170], Figs. 6-7; An, second electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 12, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 8.
An/Lee/Ogawa discloses wherein an area of the first electrode (Lee, first electrode CNE2, [0147], Fig. 7; An, first electrode 191_M, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) that is non-overlapped by the encapsulation layer (Lee, encapsulation layer PAS4, [0179], Fig. 6; An, encapsulation layer 400, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) in one of the plurality of third open areas is different from an area of the second electrode (Lee, second electrode 37, [0170], Figs. 6-7; An, second electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) that is non-overlapped by the encapsulation layer in another one of the plurality of third open areas (i.e. the area as measured in a horizontal direction in one of the plurality of third open area 351 that is non-overlapping encapsulation layer 400 is different from the first electrode 191_M to the second electrode 270, Annotated. Fig. 3; Lee, Fig. 6; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 15, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 1.
An/Lee/Ogawa discloses wherein the display panel (An, display panel DA, [0081], Fig. 1; Lee, display device 10 is a display panel, hereinafter, display panel 10, [0095], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) includes an active area in which the plurality of subpixels are disposed (An, display panel 10 includes display area DPA which is an active area, hereinafter, active area DPA, in which the plurality of subpixels SPXn are disposed, [0124], Fig. 1; Lee, display panel includes an active area DA in which the plurality of subpixels are disposed, [0095], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) and a non-active area that encloses the active area (An, non-active area NA encloses the active area DPA, [0081], Fig. 1; Lee, non-active area NDA encloses the active area DA, [0057], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1), and the active area further includes a plurality of gate driving areas that extend from the plurality of subpixels and includes a gate driver disposed therein (An, active area DPA further includes a plurality of gate driving areas that extend from the plurality of subpixels and includes a gate driver disposed therein, [0124], Fig. 1; Lee, active area DA further includes a plurality of gate driving areas that extend from the plurality of subpixels and includes a gate driver disposed therein, [0095], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 16, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 15.
An/Lee/Ogawa discloses wherein active layers of a plurality of transistors in the plurality of subpixels and active layers of a plurality of transistors in the gate driver include oxide semiconductor, amorphous silicon, or polysilicon (Lee, active layers ACT of a plurality of transistors T1 in the plurality of subpixels and active layers ACT of a plurality of transistors T2/T3 in the gate driver include oxide semiconductor, amorphous silicon, or polysilicon, [0131], Fig. 1; An, active layers 131 of a plurality of transistors TFT in the plurality of subpixels and active layers 131 of a plurality of transistors in the gate driver include oxide semiconductor, amorphous silicon, or polysilicon, [0098], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 17, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 16.
An/Lee/Ogawa discloses wherein the plurality of transistors in the gate driver include active layers of different materials (Lee, active layers ACT of the plurality of transistors T1/ T2/T3 may include different materials (i.e. oxide semiconductor, amorphous silicon, or polysilicon), [0131], Fig. 1; An, active layers 131 of the plurality of transistors TFT may include different materials (i.e. oxide semiconductor, amorphous silicon, or polysilicon), [0098], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 18, An discloses a display device (light emitting display device, [0080], Fig. 1) comprising:
a substrate (substrate 100, [0080], Fig. 1);
a thin film transistor (transistor TFT is a thin film transistor, hereinafter, thin film transistor TFT, [0096], Fig. 3) on the substrate 100 (thin film transistor TFT is on the substrate 100, [0096], Fig. 3);
a lower planarization layer (lower planarization layer 180, [0096], Fig. 3) on the thin film transistor TFT (lower planarization layer 180 is on the thin film transistor TFT, [0096], Fig. 3);
a light emitting diode (light emitting diode LED, [0096], Fig. 3) configured to emit light (light emitting diode LED is configured to emit light (i.e. emission layer 350), [0108], Fig. 3), the light emitting diode electrically connected to the thin film transistor TFT (light emitting diode LED is electrically connected to the thin film transistor TFT (i.e. pixel electrode 191 of the light emitting diode LED to the drain electrode 175 of the thin film transistor TFT), [0106], Fig. 3);
a first planarization layer (partition wall 370 is a first planarization layer, hereinafter, first planarization layer 370, [0096], Fig. 3) that encloses the light emitting diode LED (first planarization layer 370 encloses the light emitting diode LED, [0096], Fig. 3) and includes a first portion that is in direct contact with a portion of a side surface of the light emitting diode LED (first planarization layer 370 includes a first portion that is in direct contact with a portion of a side surface of the light emitting diode LED, [0096], Annotated Fig. 3) and a second portion that extends from the first portion (first planarization layer 370 includes a second portion that extends from the first portion, [0096], Annotated Fig. 3), the first portion of the first planarization layer 370 having a thickness that is less than a thickness of the second portion of the first planarization layer 370 (first portion of the first planarization layer 370 having a thickness that is less than a thickness of the second portion of the first planarization layer 370, [0096], Annotated Fig. 3).
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Annotated Fig. 3 (An) - Illustrates a first planarization layer 370 including a first portion that is in direct contact with a portion of a side surface of the light emitting diode LED and a second portion that extends from the first portion.
An does not explicitly disclose a second planarization layer that is on the light emitting diode and the first planarization layer.
However, Lee (US 2022/0302203 A1) disclose a second planarization layer (Lee, third insulating layer PAS3 is a second planarization layer, hereinafter, second planarization layer PAS3, [0178], Fig. 6; An, first planarization layer 370, [0096], Annotated Fig. 3) that is on the light emitting diode (Lee, second planarization layer PAS3 is on the light emitting diode 30, [0178], Fig. 6; An, first planarization layer 370, [0096], Annotated Fig. 3) and the first planarization layer (Lee, second planarization layer PAS3 is on the first planarization layer PAS1, [0178], Fig. 6; An, first planarization layer 370, [0096], Annotated Fig. 3). The combination to utilize an additional planarization layers near the light emitting diode allows for a resultant display device capable of preventing a short circuit or burning between wires and reducing static electricity or noise signals that may be applied externally (Lee, [0201]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an additional planarization layers near the light emitting diode to allow for a resultant display device capable of preventing a short circuit or burning between wires and reducing static electricity or noise signals that may be applied externally (Lee, [0201]).
An/Lee does not explicitly disclose a display panel including a plurality of pixels, each of the plurality of pixels including a plurality of subpixels;
A micro light emitting diode in a subpixel from the plurality of subpixels, and
Wherein the plurality of subpixels of one pixel from the plurality of pixels includes at least two subpixels configured to emit different colors from each other, and at least two subpixels configured to emit a same color as each other.
However, Ogawa (US 2023/0025876 A1) discloses a display panel (Ogawa, display device DSP is a display panel, hereinafter, display panel DSP, [0024], Fig. 1; An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1) including a plurality of pixels, each of the plurality of pixels including a plurality of subpixels (Ogawa, display panel DSP includes a plurality of pixels PX/PX/PX, each of the plurality of pixels PX/PX/PX includes a plurality of subpixels, hereinafter, plurality of subpixels SPa/SPb/SPc, [0024], Fig. 1; An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1);
a micro light emitting diode in a subpixel from the plurality of subpixels (Ogawa, micro light emitting diode 10 is in a subpixel SP from the plurality of subpixels SPa/SPb/SPc, [0024], Fig. 1; An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1), and
wherein the plurality of subpixels of one pixel from the plurality of pixels includes at least two subpixels configured to emit different colors from each other (Ogawa, the plurality of subpixels SPa/SPb/SPc of one pixel PX from the plurality of pixels PX/PX/PX includes at least two subpixels configured to emit different colors from each other (i.e. each group of subpixels within a pixel includes a red, green, and blue micro LED), [0024], Fig. 1; An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1), and at least two subpixels configured to emit a same color as each other (Ogawa, the plurality of subpixels SPa/SPb/SPc of one pixel PX from the plurality of pixels PX/PX/PX includes at least two subpixels configured to emit a same color as each other (i.e. each group of subpixels PX within a pixel includes a red, green, and blue micro LED and may emit a same color as the adjacent group of subpixels PX), [0024], Fig. 1; An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1). The combination to utilize micro light emitting diodes in combination with a plurality of adjacent subpixels ensures a resultant display device capable of improving the front luminance (Ogawa, [0134]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize micro light emitting diodes in combination with a plurality of adjacent subpixels ensures a resultant display device capable of improving the front luminance (Ogawa, [0134]).
Claim 19, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 18.
An/Lee/Ogawa discloses wherein the second planarization layer is on the first portion of the first planarization layer and the second portion of the first planarization layer (Lee, second planarization layer PAS3 is on the first portion of the first planarization layer PAS1 and the second portion of the first planarization layer PAS1, [0178], Fig. 6; An, first planarization layer 370, [0096], Annotated Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 20, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 18.
An/Lee/Ogawa discloses wherein the light emitting diode (An, light emitting diode LED, [0096], Fig. 3; Lee, light emitting element 30, [0084], Fig. 6; Ogawa, display panel DSP, [0024], Fig. 1) includes:
a first semiconductor layer (Lee, first semiconductor layer 31, [0185], Fig. 7; An, pixel electrode 191 includes a metal layer (i.e. first electrode) disposed on a transparent conductive oxide film which is a first semiconductor layer, hereinafter, first semiconductor layer 191_S, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1);
a second semiconductor layer (Lee, second semiconductor layer 32, [0186], Fig. 7; An, first semiconductor layer 191_S, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) on the first semiconductor layer (Lee, second semiconductor layer 32 is on the first semiconductor layer 31, [0186], Fig. 7; An, first semiconductor layer 191_S, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1);
an emission layer (Lee, light emitting layer 36 is an emission layer, hereinafter, emission layer 36, [0186], Fig. 7; An, emission layer 350, [0108], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) between the first semiconductor layer and the second semiconductor layer (Lee, emission layer 36 is between the first semiconductor layer 31 and the second semiconductor layer 32, [0186], Fig. 7; An, emission layer 350 is on the first semiconductor layer 191_S, [0108], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1);
a first electrode (Lee, connection electrode CNE2 is a first electrode, hereinafter, first electrode CNE2, [0147], Fig. 7; An, pixel electrode 191 includes a metal layer which is a first electrode, hereinafter, first electrode 191_M, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) on the first semiconductor layer (Lee, first electrode CNE2 is on the first semiconductor layer 31, [0147], Figs. 6-7; An, first electrode 191_M is on the first semiconductor layer 191_S, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) and is spaced apart from the emission layer (Lee, first electrode CNE2 is spaced apart from the emission layer 36, [0186], Figs. 6-7; An, first electrode 191_M is spaced apart from the emission layer 350, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1);
a second electrode (Lee, electrode layer 37 is a second electrode, hereinafter, second electrode 37, [0170], Figs. 6-7; An, common electrode 270 is a second electrode, hereinafter, second electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) on the second semiconductor layer (Lee, second electrode 37 is on the second semiconductor layer 32, [0170], Figs. 6-7; An, second electrode 270 is on the first semiconductor layer 191_S and would include a second semiconductor layer if second electrode 270 utilized a similar multilayer structure as utilized by the first electrode 191_M, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1); and
an encapsulation layer (Lee, fourth insulating layer PAS4 is an encapsulation layer, hereinafter, encapsulation layer PAS4, [0179], Fig. 6; An, encapsulation layer 400, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) that encloses a first part of a side surface of the first semiconductor layer (Lee, encapsulation layer PAS4 encloses the entirety of the first semiconductor layer 31, [0179], Fig. 6; An, encapsulation layer 400 encloses the entirety of the first semiconductor layer 191_S, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1), the emission layer (Lee, encapsulation layer PAS4 encloses the emission layer 36, [0186], Fig. 7; An, encapsulation layer 400 encloses the emission layer 350, [0108], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1), the second semiconductor layer (Lee, encapsulation layer PAS4 encloses the second semiconductor layer 32, [0186], Fig. 7; An, encapsulation layer 400, [0108], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1), the first electrode (Lee, encapsulation layer PAS4 encloses the first electrode 191_M, [0186], Fig. 7; An, encapsulation layer 400 encloses the first electrode 191_M, [0108], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1), and the second electrode (Lee, encapsulation layer PAS4 encloses second electrode 37, [0170], Figs. 6-7; An, encapsulation layer 400 encloses the second electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1).
An/Lee does not explicitly disclose a micro light emitting diode.
However, Ogawa (US 2023/0025876 A1) discloses a micro light emitting diode (Ogawa, micro light emitting diode 10, [0024], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1). The combination to utilize micro light emitting diodes in combination with a plurality of adjacent subpixels ensures a resultant display device capable of improving the front luminance (Ogawa, [0134]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize micro light emitting diodes in combination with a plurality of adjacent subpixels ensures a resultant display device capable of improving the front luminance (Ogawa, [0134]).
Claim 22, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 20.
An/Lee/Ogawa discloses further comprising:
a first connection electrode (Lee, first connection electrode CNE1, [0178], Figs. 6-7; An, common electrode 270 is a second electrode, hereinafter, second electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) in contact with the second electrode (Lee, electrode layer 37 is a second electrode, hereinafter, second electrode 37, [0170], Figs. 6-7; An, second electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1); and
a second connection electrode (Lee, second electrode 22 is a second connection electrode, hereinafter, second connection electrode 22, [0170], Figs. 6-7; An, drain electrode 175 is a second connection electrode, hereinafter, second connection electrode 175, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) in contact with the first electrode (Lee, second connection electrode 22 is in contact with the first electrode CNE2, [0157], Figs. 6-7; An, second connection electrode 175 is in contact with the first electrode 191_M, [0096], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) to electrically connect the light emitting diode with the thin film transistor (Lee, second connection electrode 22 is in contact with the first electrode CNE2 to electrically connect the light emitting diode 30 with the thin film transistor T1 (i.e. first transistor T1), [0157], Figs. 6-7; An, second connection electrode 175 is in contact with the first electrode 191_M to electrically connect the light emitting diode LED with the thin film transistor TFT, [0096], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1).
Claim 23, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 22.
An/Lee/Ogawa discloses wherein the first connection electrode (Lee, first connection electrode CNE1, [0178], Figs. 6-7; An, common electrode 270 is a second electrode, hereinafter, second electrode 270, [0109], Fig. 3) and the second connection electrode (Lee, second connection electrode 22, [0170], Figs. 6-7; An, second connection electrode 175, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) are in direct contact with the first portion of the first planarization layer (Lee, first connection electrode CNE1 and second connection electrode 22 are in direct contact with the first planarization layer PAS3 (i.e. first planarization layer PAS3 has a first portion and a second portion with varying thicknesses), [0178], Figs. 6-7; An, second electrode 270 is in direct contact with the first portion of the first planarization layer (i.e. when interlayer insulating layer 160 is the lower planarization layer, interlayer insulating layer 160 and lower planarization layer 180 may together constitute a first planarization layer having a first and second portion with varying thicknesses), [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1). The combination to enclose all electrically conductive elements in insulating/planarization materials allows for the planarization of the light emitting surface and blocking penetration of impurities (An, [0097]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to enclose all electrically conductive elements in insulating/planarization materials allows for the planarization of the light emitting surface and blocking penetration of impurities (An, [0097]).
Claim 24, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 1.
An/Lee/Ogawa wherein the first planarization layer has a step formed by a difference between the first thickness and the second thickness (An; first planarization layer 370 has a step formed by a difference between the first thickness and the second thickness, [0096], Annotated Fig. 3; Lee, first planarization layer PAS3; Ogawa, display panel DSP, [0024], Fig. 1).
Claims 6, 10, 13, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over An in view of Lee, and further in view of Son (US 2020/0212026 A1).
Claim 6, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 5.
An/Lee/Ogawa does not explicitly disclose wherein a second part of the side surface of the first semiconductor layer is non-overlapping with the encapsulation layer in the first open area and the first planarization layer is in contact with the second part of the side surface that is non-overlapping with the encapsulation layer.
However, Son (US 2020/0212026 A1) discloses wherein a second part of the side surface of the first semiconductor layer (Son, n-type layer 141 is a first semiconductor layer, hereinafter, first semiconductor layer 141 and comprises a second part of the side surface of the first semiconductor layer 141 that is overlapping with the first connecting unit 155 and the second connecting unit 156, hereinafter, second part of the side surface of the first semiconductor layer 141/155/156, [0063], Fig. 3; Lee, first semiconductor layer 31, [0185], Fig. 7; An, first semiconductor layer 191_S, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) is non-overlapping with the encapsulation layer (Son, second part of the side surface of the first semiconductor layer 141/155/156 is non-overlapping with the encapsulation layer 150, [0063], Fig. 3; Lee, first semiconductor layer 31, [0179], Fig. 6; An, first semiconductor layer 191_S, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) and the first planarization layer (Son, adhesive layer 133 is a first planarization layer, hereinafter, first planarization layer 133, [0052], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) is in direct contact with the second part of the side surface that is non-overlapping with the encapsulation layer (Son, first planarization layer 133 is in direct contact with the second part of the side surface 141/155/156 that is non-overlapping with the encapsulation layer 150, [0052], Fig. 3; Lee, first planarization layer PAS1, [0178], Fig. 6; An, first planarization layer 370 is in direct contact with the first semiconductor layer 191_S that is non-overlapping with the encapsulation layer 400 (i.e. non-overlapping in the horizontal direction), [0096], Annotated Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1). The combination to utilize a light emitting diode structure in combination with the non-overlapping and overlapping encapsulation layers would allow for specific connecting units to electrically connect the light emitting diode and allow for smooth connections (i.e. preventing electrical shorting, etc.) (Son, [0074]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a light emitting diode structure in combination with the non-overlapping and overlapping encapsulation layers to allow for specific connecting units to electrically connect the light emitting diode and allow for smooth connections (i.e. preventing electrical shorting, etc.) (Son, [0074]).
Claim 10, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 8.
An/Lee/Ogawa does not explicitly disclose wherein the second planarization layer further includes a dummy open area that is non-overlapping with the first electrode and the second electrode.
However, Son discloses disclose wherein the second planarization layer (Son, planarization layer 150, [0052], Fig. 3; Lee, second planarization layer PAS3, [0178], Fig. 6; An, first planarization layer 370, [0096], Annotated Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) further includes a dummy open area that is non-overlapping with the first electrode and the second electrode (Son, planarization layer 150 further includes a dummy open area H1/H2 that is non-overlapping with the first electrode 555 and the second electrode 556, [0088], Fig. 3; Lee, second planarization layer PAS3, [0178], Fig. 6; An, first planarization layer 370, [0096], Annotated Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1). The combination to utilize additional routing hole in combination with a dummy open area enables a stable connection to be provided between electrically isolated structures (Son, [0085]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize additional routing holes in combination with a dummy open area enables a stable connection to be provided between electrically isolated structures (Son, [0085]).
Claim 13, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 8.
An/Lee/Ogawa discloses wherein the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) further comprising:
a reflection plate (Lee, electrodes 21 and 22 function as a reflection plate, hereinafter, reflection plate 21/22, [0149], Fig. 6; An, Annotated Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) connected to a pixel circuit of the display panel (Lee, reflection plate 21/22 is connected to a pixel circuit (i.e. first transistor T1, [0083]) of the display panel, [0149], Fig. 6; An, Annotated Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1), the reflection plate in contact with the connection electrode (Lee, reflection plate 21/22 is in contact with the first connection electrode CNE1, [0178], Figs. 6-7; An, connection electrode 270, [0109], Fig. 3) through the fourth open area (Lee, reflection plate 21/22 is in contact with the first connection electrode CNE1 through the fourth open area OP, [0178], Figs. 6-7; An, connection electrode 270, [0109], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1).
An/Lee/Ogawa does not explicitly disclose wherein the second planarization layer further includes a fourth open area though an entire thickness of the second planarization layer.
However, Son discloses wherein the second planarization layer 150 further includes a fourth open area 155B/156A/156B though an entire thickness of the second planarization layer 150 ([0080], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1). The combination to include a fourth open area through an entire thickness of an above lying planarization layer ensures formation of reliable electrical connections as vias (Son, [0081]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to include a fourth open area through an entire thickness of an above lying planarization layer to ensure formation of reliable electrical connections as vias (Son, [0081]).
Claim 21, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 20.
An/Lee/Ogawa does not explicitly disclose wherein a second part of the side surface of the first semiconductor layer is non-overlapping with the encapsulation layer and the first planarization layer is in direct contact with the second part of the side surface that is non-overlapping with the encapsulation layer.
However, Son (US 2020/0212026 A1) discloses wherein a second part of the side surface of the first semiconductor layer (Son, n-type layer 141 is a first semiconductor layer, hereinafter, first semiconductor layer 141 and comprises a second part of the side surface of the first semiconductor layer 141 that is overlapping with the first connecting unit 155 and the second connecting unit 156, hereinafter, second part of the side surface of the first semiconductor layer 141/155/156, [0063], Fig. 3; Lee, first semiconductor layer 31, [0185], Fig. 7; An, first semiconductor layer 191_S, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) is non-overlapping with the encapsulation layer (Son, second part of the side surface of the first semiconductor layer 141/155/156 is non-overlapping with the encapsulation layer 150, [0063], Fig. 3; Lee, first semiconductor layer 31, [0179], Fig. 6; An, first semiconductor layer 191_S, [0106], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) and the first planarization layer (Son, adhesive layer 133 is a first planarization layer, hereinafter, first planarization layer 133, [0052], Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1) is in direct contact with the second part of the side surface that is non-overlapping with the encapsulation layer (Son, first planarization layer 133 is in direct contact with the second part of the side surface 141/155/156 that is non-overlapping with the encapsulation layer 150, [0052], Fig. 3; Lee, first planarization layer PAS1, [0178], Fig. 6; An, first planarization layer 370 is in direct contact with the first semiconductor layer 191_S that is non-overlapping with the encapsulation layer 400 (i.e. non-overlapping in the horizontal direction), [0096], Annotated Fig. 3; Ogawa, display panel DSP, [0024], Fig. 1). The combination to utilize a light emitting diode structure in combination with the non-overlapping and overlapping encapsulation layers would allow for specific connecting units to electrically connect the light emitting diode and allow for smooth connections (i.e. preventing electrical shorting, etc.) (Son, [0074]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a light emitting diode structure in combination with the non-overlapping and overlapping encapsulation layers to allow for specific connecting units to electrically connect the light emitting diode and allow for smooth connections (i.e. preventing electrical shorting, etc.) (Son, [0074]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over An in view of Lee, and further in view of Lee (US 2023/0035525 A1), hereinafter, Lee*.
Claim 4, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 3.
An/Lee/Ogawa does not explicitly disclose wherein the first planarization layer is formed by photolithography using a halftone mask.
However, Lee* (US 2023/0035525 A1) discloses wherein the first planarization layer (passivation layer 3 is a first planarization layer, hereinafter, first planarization layer 3, [0060], Fig. 8) is formed by photolithography using a halftone mask (first planarization layer 3 is formed by photolithography using photoresist layer 5 which is a halftone mask, hereinafter, halftone mask 5, [0060], Fig. 8). The combination to utilize a halftone photoresist mask to form a planarization layer prevents excessive etching from affecting the other parts of the planarization layer (Lee*, [0062]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a halftone photoresist mask to form a planarization layer to prevent excessive etching from affecting the other parts of the planarization layer (Lee*, [0062]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over An in view of Lee, in view of Ogawa, and further in view of Chen (US 2022/0384677 A1).
Claim 14, An/Lee/Ogawa discloses the display device (An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1) according to claim 5.
An/Lee/Ogawa does not explicitly disclose further comprising:
an adhesive layer between the display panel and the micro light emitting diode,
wherein a bottom surface of the first semiconductor layer is in contact with the adhesive layer, and
wherein the bottom surface of the first semiconductor layer includes a plurality of convex portions and a plurality of concave portions.
However, Chen (US 2022/0384677 A1) discloses further comprising:
an adhesive layer between the display panel and the micro light emitting diode (Chen, adhesive layer 300/500 between the display panel 100 and the micro light emitting diode 200, [0174], Fig. 13; An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1),
wherein a bottom surface of the first semiconductor layer is in contact with the adhesive layer (Chen, a bottom surface of the first semiconductor layer 211 (i.e. including 212, 213, and 220) is in contact with the adhesive layer 300/500, [0174], Fig. 13; An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1), and
wherein the bottom surface of the first semiconductor layer includes a plurality of convex portions and a plurality of concave portions (Chen, the bottom surface of the first semiconductor layer 211 includes a plurality of convex portions and a plurality of concave portions, [0174], Fig. 13; An, light emitting display device, [0080], Fig. 1; Lee, display device 10, [0053], Fig. 1; Ogawa, display panel DSP, [0024], Fig. 1). The combination to utilize an adhesive layer with a semiconductor layer of a micro LED epitaxial structure as well as a plurality of underlying convex and concave portions forms a concave-convex microstructure, which makes it easier to generate the point discharge, the inspection efficiency may be improved (Chen, [0110]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an adhesive layer with a semiconductor layer of a micro LED epitaxial structure as well as a plurality of underlying convex and concave portions to form a concave-convex microstructure, which makes it easier to generate the point discharge, the inspection efficiency may be improved (Chen, [0110]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee* (US 2023/0035525 A1) discloses the display device (display panel 10, [0044], Fig. 2), wherein a bottom surface of the first semiconductor layer includes a plurality of convex portions and a plurality of concave portions (bottom surface of light filter layer 1 includes a plurality of convex-concave portions (i.e. concave-convex structure 31), [0045], Fig. 2).
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Annotated Fig. 2 (Lee*) – Illustrates wherein a bottom surface of light filter layer 1 includes a plurality of convex-concave portions (i.e. concave-convex structure 31.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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