DETAILED ACTION
This Notice is responsive to communication filed on 07/29/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I Invention, reading on claims 1-14 in the reply filed on 07/29/2026 is acknowledged.
Claims withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/29/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/01/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the first conductive structure" in line 1. There is insufficient antecedent basis for this limitation in the claim. Claim 3 will be interpreted as “the first conductive region” for the purpose of examination in this Office Action.
Claim 8 recites the limitation "he first additional conductive region" in lines 4-5. There is insufficient antecedent basis for this limitation in the claim. Claim 8 will be interpreted as “the first conductive region” for the purpose of examination in this Office Action.
Claim 12 recites the limitation "the conductive portion" in line 1. There is insufficient antecedent basis for this limitation in the claim. Claim 12, depending from claim 1, will be interpreted as “a second portion” for the purpose of examination in this Office Action, due to the second portion as claimed in claim 1 including conductive material.
Claim 13 recites the limitation "the conductive portion " in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 13, depending from claim 1, will be interpreted as “a second portion” for the purpose of examination in this Office Action, due to the second portion as claimed in claim 1 including conductive material.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-11, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karda et al. (US 20210066196).
Regarding claim 1, Karda discloses an apparatus comprising:
a first conductive region Fig. 7: 297;
a second conductive region Fig. 7: 221;
a memory cell Fig. 7: 210 (para. 0023) between the first Fig. 7: 297 and second conductive regions Fig. 7: 221, the memory cell Fig. 7: 210 including:
a first transistor Fig. 7: T1 including a first region (para. 0036, channel region of T1) coupled to the first Fig. 7: 297 and second Fig. 7: 221 conductive regions, and a charge storage structure Fig. 7: 202 (para. 0026) separated from the first conduction region Fig. 7: 297; and
a second transistor Fig. 7: T2 including a second region (para. 0026 channel region of T2) coupled to the charge storage structure Fig. 7: 202 and the second conductive region Fig. 7: 221;
a structure Fig. Fig. 7: 241 (para. 0029-0030) separated from the first region, the charge storage structure Fig. 7: 202, and the second region by a dielectric structure Fig. 8: 518F/B,
the structure Fig. 7: 241 forming part of a gate of the first transistor and the second transistor (para. 0031), and the structure Fig. 7: 241 including:
a first portion Fig. 7: 541B (para. 0071-0073) adjacent the dielectric structure, and
a second portion Fig. 7: 541F adjacent the first portion Fig. 7: 541B, wherein the first portion Fig. 7: 541B includes a semiconductor material and the second portion Fig. 7: 541F includes a conductive material (para. 0072 teaches conductive materials and also polysilicon which is a semiconductor material).
Regarding claim 2, Karda discloses the apparatus of claim 1, wherein the second conductive region Fig. 7: 221 is part of a data line of the apparatus (para. 0030).
Regarding claim 3, Karda discloses the apparatus of claim 1, wherein the first conductive region Fig. 7: 297 (see 112 rejections above regarding interpretation of “the first conductive structure”) is part of a ground connection of the apparatus (para. 0035).
Regarding claim 4, Karda discloses the apparatus of claim 1, wherein the first region includes a channel region of the first transistor Fig. 7: T1, and the second region includes a channel region of the second transistor Fig. 7: T2 (para. 0024).
Regarding claim 5, Karda discloses the apparatus of claim 1, wherein the first and second regions (i.e. of T1 and T2) include materials having different conductivity types (para. 0024 teaches a PFET and NFET of the transistors T1 and T2 which have different conductivity types).
Regarding claim 6, Karda discloses the apparatus of claim 1, wherein the second region (of T2) comprises a semiconducting oxide material (para. 0024 teaches “n-channel metal-oxide semiconductor”).
Regarding claim 7, Karda discloses the apparatus of claim 1, wherein the semiconductor material of the first portion Fig. 7: 541B includes polysilicon (para. 0072).
Regarding claim 8, Karda discloses the apparatus of claim 1, further comprising:
a second additional conductive region Fig. 7: 222 separated from the first conductive region Fig. 7: 297; and
an additional memory cell Fig. 7: 211 (para. 0027), the additional memory cell Fig. 7: 211 including:
a first additional transistor Fig. 7: T1 (corresponding to 211) including a first additional region coupled to the first conductive region Fig. 7: 297 (see 112 rejections above regarding interpretation of “the first additional conductive region”) and the second conductive region Fig. 7: 221, and an additional charge storage structure Fig. 7: 202 (corresponding to 211) separated from the first additional region (shown in Fig. 7); and
a second additional transistor Fig. 7: T2 (corresponding to 211) including a second additional region coupled to the additional charge storage structure Fig. 7: 202 and the second additional conductive region Fig. 7: 222, wherein:
the structure Fig. 7: 241 forms part of a gate of the first additional transistor Fig. 7: T1 and the second additional transistor Fig. 7: T2 (para. 0031).
Regarding claim 9, Karda discloses the apparatus of claim 1, further comprising an additional memory cell Fig. 7: 211, wherein the memory cell Fig. 7: 210 is included in a first deck of memory cells of the apparatus, the additional memory cell Fig. 7: 211 is included in a second deck of additional memory cells of the apparatus, and the first deck of memory cells and the second deck of memory cells are located in different levels of the apparatus (para. 0027 teaches the different groups of memory cells and Fig. 2 shows the different levels).
Regarding claim 10, Karda discloses an apparatus comprising:
a first conductive region Fig. 7: 297 located in a first level of the apparatus;
a second conductive region Fig. 7: 221 located in a second level of the apparatus;
a memory cell Fig. 7: 210 located between the first and second levels and coupled to the first Fig. 7: 297 and second Fig. 7: 221 conductive regions, the memory cell Fig. 7: 210 including:
a memory element Fig. 7: 202 (para. 0025 teaches memory element) located in a third level of the apparatus between the first and second levels; and
a channel region Fig. 7: 520 (para. 0079 teaches channel region) located in a fourth level of the apparatus between the second and third levels and coupled to the second conductive region Fig. 7: 221 and the memory element Fig. 7: 202;
a first semiconductor material Fig. 510A/B (para. 0087) located between the first and second levels and coupled to the first Fig. 7: 297 and second Fig. 7: 221 conductive regions;
a dielectric structure Fig. 7: 518A/518B (para. 0089) adjacent the memory element Fig. 7: 202, the channel region Fig. 7: 520, and a semiconductor material Fig. 510A, the dielectric structure Fig. 7: 518A/518B including a dielectric material having a dielectric constant greater than a dielectric constant of silicon dioxide (para. 0089 teaches dielectric constant greater); and
a semiconductor portion Fig. 7: 541B adjacent the dielectric structure Fig. 7: 518A/518B;
a conductive portion Fig. 7: 541F adjacent the semiconductor portion, wherein the semiconductor portion Fig. 7: 541B is between the dielectric structure Fig. 7: 518A/518B and the conductive portion Fig. 7: 541F (see Fig. 21 for this arrangement).
Regarding claim 11, Karda discloses the apparatus of claim 1, wherein the semiconductor material Fig. 7: 541B includes polysilicon (para. 0072).
Regarding claim 14, Karda discloses the apparatus of claim 10, wherein the second conductive region Fig. 7: 221 is part of a data line of the apparatus (para. 0030 teaches data line 221), and the conductive portion Fig. 7: 541F is part of a word line of the apparatus (para. 0073 teaches 541F and 541B are part of a single access line 241, and the present disclosure interchanges the access line with word line).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claim(s) 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Karda et al. (US 20210066196) as applied to claim 1 above, and further in view of Takeguchi (US 20140367804).
Regarding claim 12, Takeguchi discloses the following claim limitations not disclosed by Karda, the apparatus of claim 1, wherein:
the conductive portion (interpreted as the second portion, per the 112 rejections above) includes at least one of titanium nitride and tungsten.
Takeguchi teaches a gate structure comprised of polysilicon, silicide, and tungsten, where the silicide layer comprises titanium nitride (para. 0006-0008).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Karda’s teachings with Takeguchi’s in order to reduce interface resistance and also reduce sheet resistance (abstract).
Regarding claim 13, Karda discloses the apparatus of claim 1, wherein:
the dielectric structure Fig. 7: 518F/B includes aluminum oxide (para. 0095),
the semiconductor material (of the first portion of claim 1) includes polysilicon (para. 0072), and
the conductive portion (interpreted as the second portion, per the 112 rejections above) includes at least one of titanium nitride and tungsten.
Takeguchi discloses the following claim limitations not disclosed by Karda:
the conductive portion (interpreted as the second portion, per the 112 rejections above) includes at least one of titanium nitride and tungsten.
Takeguchi teaches a gate structure comprised of polysilicon, silicide, and tungsten, where the silicide layer comprises titanium nitride (para. 0006-0008).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Karda’s teachings with Takeguchi’s in order to reduce interface resistance and also reduce sheet resistance (abstract).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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