Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
1. Applicant’s election without traverse of Species I in the reply filed on 5/6/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17, 19, and 21-32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2023/0136514 Jiang et al.
2. Referring to claim 17, Jiang et al. teaches a manufacturing method for a semiconductor device, comprising: forming a FEOL (Front End of Line) structure, (Figure 15 #200 & Paragraph 0021); forming a transistor, comprising: forming a back gate, (Figure 15 #210), on the FEOL structure, (Figure 15 #200 & Paragraph 0021); forming an active channel layer, (Figure 15 #231), on the back gate, (Figure 15 #210); forming a first dielectric layer, (Figure 15 #240), over the active channel layer, (Figure 15 #231); forming a first blocking layer, (Figure 15 #270), on the first dielectric layer, (Figure 15 #240), wherein the first blocking layer, (Figure 15 #270), overlaps the active channel layer, (Figure 15 #231); and forming an electrode, (Figure 15 #250), electrically connected to the active channel layer, (Figure 15 #231).
3. Referring to claim 19, Jiang et al. teaches a manufacturing method as claimed in claim 17, wherein in forming the electrode, (Figure 15 #250), electrically connected to the active channel layer, (Figure 15 #231), the first blocking layer, (Figure 15 #270), has a lateral surface, and the lateral surface and the electrode, (Figure 15 #250), are spaced from each other.
4. Referring to claim 21, Jiang et al. teaches a manufacturing method as claimed in claim 17, wherein in forming the transistor, the manufacturing method further comprises: forming a second dielectric layer, (Figure 15 #221), on the active channel layer, (Figure 15 #231).
5. Referring to claim 22, Jiang et al. teaches a manufacturing method as claimed in claim 21, wherein the second dielectric layer, (Figure 15 #221), is disposed between the active channel layer, (Figure 15 #231), and the back gate, (Figure 15 #210).
6. Referring to claim 23, Jiang et al. teaches a manufacturing method as claimed in claim 21, wherein in forming the active channel layer, (Figure 15 #231), on the back gate, (Figure 15 #210), the active channel layer, (Figure 15 #231), is contact with the second dielectric layer, (Figure 15 #221).
7. Referring to claim 24, Jiang et al. teaches a manufacturing method as claimed in claim 17, wherein in forming the electrode, (Figure 15 #250), electrically connected to the active channel layer, (Figure 15 #221), the electrode, (Figure 15 #250), has a second upper surface flush with a first upper surface of the first dielectric layer, (Figure 15 #240).
8. Referring to claim 25, Jiang et al. teaches a manufacturing method as claimed in claim 17, wherein in forming the first blocking layer, (Figure 15 #270), on the first dielectric layer, (Figure 15 #240), the first blocking layer, (Figure 15 #270), protrudes relative to a first upper surface of the first dielectric layer, (Figure 15 #240).
9. Referring to claim 26, Jiang et al. teaches a manufacturing method for a semiconductor device, comprising: forming a FEOL structure, (Figure 15 #200 & Paragraph 0021); forming a transistor, comprising: forming a back gate, (Figure 15 #210), on the FEOL structure, (Figure 15 #200 & Paragraph 0021); forming an active channel layer, (Figure 15 #231), on the back gate, (Figure 15 #210), wherein the active channel layer, (Figure 15 #231), is formed of a material comprising CuO, SnO, InO, IZO, IGO, IGZO, IWO, IWZO, (Paragraph 0027); forming a first dielectric layer, (Figure 15 #240), over the active channel layer, (Figure 15 #231); forming a first blocking layer, (Figure 15 #270), on the first dielectric layer, (Figure 15 #240), wherein the first blocking layer, (Figure 15 #270), overlaps the active channel layer, (Figure 15 #231,; and forming an electrode, (Figure 15 #250), electrically connected to the active channel layer, (Figure 15 #231).
10. Referring to claim 27, Jiang et al. teaches a manufacturing method as claimed in claim 26, wherein in forming the electrode, (Figure 15 #250), electrically connected to the active channel layer, (Figure 15 #231), the first blocking layer, (Figure 15 #270), has a lateral surface, and the lateral surface and the electrode, (Figure 15 #250), are spaced from each other.
11. Referring to claim 28, Jiang et al. teaches a manufacturing method as claimed in claim 26, wherein in forming the transistor, the manufacturing method further comprises: forming a second dielectric layer, (Figure 15 #221), on the active channel layer, (Figure 15 #231).
12. Referring to claim 29, Jiang et al. teaches a manufacturing method as claimed in claim 28, wherein the second dielectric layer, (Figure 15 #221), is disposed between the active channel layer, (Figure 15 #231), and the back gate, (Figure 15 #210).
13. Referring to claim 30, Jiang et al. teaches a manufacturing method as claimed in claim 28, wherein in forming the active channel layer, (Figure 15 #231), on the back gate, (Figure 15 #210), the active channel layer, (Figure 15 #231), is contact with the second dielectric layer, (Figure 15 #221).
14. Referring to claim 31, Jiang et al. teaches a manufacturing method as claimed in claim 26, wherein in forming the electrode, (Figure 15 #250), electrically connected to the active channel layer, (Figure 15 #231), the electrode, (Figure 15 #250), has a second upper surface flush with a first upper surface of the first dielectric layer, (Figure 15 #240).
15. Referring to claim 32, Jiang et al. teaches a manufacturing method as claimed in claim 26, wherein in forming the first blocking layer, (Figure 15 #270), on the first dielectric layer, (Figure 15 #240), the first blocking layer, (Figure 15 #270), protrudes relative to a first upper surface of the first dielectric layer, (Figure 15 #240).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 33-38 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. U.S. Patent Application Publication No. 2023/0136514 Jiang et al. in view of U.S. Patent Application Publication No. 2022/0393033 Van Dal et al.
16. Referring to claim 33, Jiang et al. teaches a manufacturing method for a semiconductor device, comprising: forming a FEOL structure; forming a transistor, comprising: forming a back gate, (Figure 15 #210), on the FEOL structure; forming an active channel layer, (Figure 15 #231), on the back gate, (Figure 15 #210); forming a first dielectric layer, (Figure 15 #240), over the active channel layer, (Figure 15 #231); forming a first blocking layer, (Figure 15 #270 Paragraph 0033 hydrogen absorbing layer), on the first dielectric layer, (Figure 15 #240), wherein the first blocking layer, (Figure 15 #270), overlaps the active channel layer, (Figure 15 #231), and is formed of an insulation material; and forming an electrode, (Figure 15 #250), electrically connected to the active channel layer, (Figure 15 #231), but is silent to the first blocking layer is formed of an insulation material.
Van Dal et al. teaches a similar device where a hydrogen blocking layer is formed of an insulation material, (Paragraph 0048).
The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Van Dal et al. with Jiang et al. because it is well known in the art that a hydrogen blocking layer is formed of an insulation material, and also since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice.
In re Leshin, 125 USPQ 416.
17. Referring to claim 34, Jiang et al. in view of Van Del et al. teaches a manufacturing method as claimed in claim 33, wherein in forming the electrode, (Figure 15 #250), electrically connected to the active channel layer, (Figure 15 #231), the first blocking layer, (Figure 15 #270), has a lateral surface, and the lateral surface and the electrode, (Figure 15 #250), are spaced from each other.
18. Referring to claim 35, Jiang et al. in view of Van Del et al. teaches a manufacturing method as claimed in claim 33, wherein in forming the transistor, the manufacturing method further comprises: forming a second dielectric layer, (Figure 15 #221), on the active channel layer, (Figure 15 #231).
19. Referring to claim 36, Jiang et al. in view of Van Del et al. teaches a manufacturing method as claimed in claim 35, wherein the second dielectric layer, (Figure 15 #221), is disposed between the active channel layer, (Figure 15 #231), and the back gate, (Figure 15 #210).
20. Referring to claim 37, Jiang et al. in view of Van Del et al. teaches a manufacturing method as claimed in claim 35, wherein in forming the active channel layer, (Figure 15 #231), on the back gate, (Figure 15 #210), the active channel layer, (Figure 15 #231), is contact with the second dielectric layer, (Figure 15 #221).
21. Referring to claim 38, Jiang et al. in view of Van Del et al. teaches a manufacturing method as claimed in claim 33, wherein in forming the electrode, (Figure 15 #250), electrically connected to the active channel layer, (Figure 15 #231), the electrode, (Figure 15 #250), has a second upper surface flush with a first upper surface of the first dielectric layer, (Figure 15 #240).
Conclusion
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/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 7/1/26
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