Prosecution Insights
Last updated: July 17, 2026
Application No. 18/433,254

IMAGE SENSING DEVICE INCLUDING SLOPED ISOLATION STRUCTURE

Non-Final OA §102§112
Filed
Feb 05, 2024
Priority
Sep 05, 2023 — RE 10-2023-0117997
Examiner
LEE, EUGENE
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
742 granted / 907 resolved
+13.8% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
43 currently pending
Career history
944
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
73.6%
+33.6% vs TC avg
§102
10.7%
-29.3% vs TC avg
§112
2.6%
-37.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 907 resolved cases

Office Action

§102 §112
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Species I, Subspecies I (FIG. 8A, claims 1-10, 13, and 15-18) in the reply filed on 6/8/26 is acknowledged. Claims 11, 12, 14, 19, and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/8/26. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1 thru 10, 13, and 15 thru 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In line 8 of claim 1, the applicant states a “a plurality of circuit structures”, but in line 5, the applicant states “a plurality of unit pixel regions”; however, it is unclear (see, for example, FIG.3) whether the plurality of circuit structures 320 and the plurality of unit pixel regions 100/200 are the same structure. In paragraph [0044], the applicant states the unit pixel may include a photoelectric conversion region 100 and a circuit region 200, but the plurality of circuit structures 320 are part of the photoelectric conversion region 100, and, therefore, part of the plurality of unit pixel regions, and therefore, it is unclear whether the plurality of circuit structures 320 are actually distinct from the unit pixel regions 100/200 as stated in the claim. Appropriate clarification and/or correction are required. In lines 12-13 of claim 1, the applicant states “a first isolation structure disposed between adjacent unit pixel regions of the plurality of unit pixel region in the substrate,”; however, it appears (see, for example, FIG. 8A) the first isolation structure 336b’/336a’ is disposed in the circuit region 200 and photoelectric conversion region 100, and not disposed between adjacent unit pixel regions 100/200. Further, the term “first isolation structure” is not used in applicant’s specification, and is arbitrarily defined by the Examiner as any region that has an isolation structure, but what actual structure (see, for example, in FIG. 8A) the applicant is referring to is unclear. The same applies to claim 16. Appropriate clarification and/or correction are required. In lines 16-17 of claim 1, the applicant states “a plurality of second isolation structures located on two opposite sides of the plurality of circuit structures”; however, it appears (see, for example, FIG. 8A) the plurality of second isolation structures 336b’/336a’ are not located on two opposite sides of the plurality of circuit structures 200. Further, the term “second isolation structures” is not used in applicant’s specification, and is arbitrarily defined by the Examiner as regions that have isolation structures, but what actual structure (see, for example, in FIG. 8A) the applicant is referring to is unclear. The same applies to claim 16 which states “a second isolation structure”. Appropriate clarification and/or correction are required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. In view of the 112 rejection above, claim(s) 1 thru 3, 13, and 15 thru 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong et al. US 2020/0111821 A1. Hong discloses (see, for example, FIG. 2, and 1) an image sensing device comprising: a substrate 1 structured to extend in a first direction (i.e. x-direction) and a second direction (y-direction) perpendicular to the first direction and configured to include a first surface 1b and a second surface 1a opposite to the first surface; a plurality of unit pixel regions UP1/UP2 supported by the substrate 1 and configured to generate signal carriers through conversion of incident light; a plurality of circuit structures PD1 supported by the substrate 1 and arranged to be spaced apart from each other in the first direction and configured to generate a current in the substrate 1 and capture the signal carriers carried by the current; a first isolation structure STI disposed between adjacent unit pixel regions of the plurality of unit pixel regions UP1/UP2 in the substrate 1, and configured to extend vertically in a depth direction of the substrate while extending in the second direction; and a plurality of second isolation structures DTI located on two opposite sides of the plurality of circuit structures PD1 in the second direction within the substrate 1, and arranged to extend obliquely in a depth direction in the substrate while extending in the first direction. Regarding the limitation “a plurality of second isolation structures … arranged to extend obliquely in a depth direction”, Hong discloses (see, for example, paragraph [0026]) the plurality of second isolation structures DTI has a width that decreases as if approaches the second surface 1a from the first surface 1b. Regarding claim 2, see, for example, FIG. 2 wherein Hong discloses the second isolation structures DTI include: a first sloped isolation structure 9/7 extending obliquely from one side of the plurality of circuit structures PD1 in a first diagonal direction; and a second sloped isolation structure 9/7 extending obliquely from opposite sides of the plurality of circuit structures PD1 in a second diagonal direction symmetrical to the first diagonal direction. Regarding claim 3, see, for example, FIG. 2 wherein Hong discloses the second isolation structures 9/7 are arranged to be inclined such that a spacing between the first sloped isolation structure 9/7 and the second sloped isolation structure 9/7 tapers from the first surface 1b toward the second surface 1a. Regarding claim 13, see, for example, FIG. 2 wherein Hong discloses the first sloped isolation structure 9/7 and the second sloped isolation structure 9/7 extend in the first direction while uniformly maintaining a spacing between the first sloped isolation structure 9/7 and the second sloped isolation structure 9/7 within a unit pixel. Regarding claim 15, see, for example, FIG. 2 wherein Hong discloses the first isolation structure 9/7 extends vertically from the first surface 1b toward the second surface 1a to overlap the circuit structures PD1. Regarding claim 16, see, for example, FIG. 2 wherein Hong discloses an image sensing device comprising: a substrate 1 extending in a first direction (i.e. x-direction) and a second direction (y-direction) perpendicular to the first direction and including a first surface 1b and a second surface 1a opposite to the first surface 1b; a plurality of circuit structures FD1 arranged to be spaced apart from each other in the first direction on the second surface 1a of the substrate 1, and configured to generate a current in the substrate and capture the signal carriers moving by the current; first pixel transistors TG1 disposed at one side of the plurality of circuit structures FD1 in the second direction on the second surface 1a of the substrate 1; second pixel transistors TG1 disposed at opposite sides of the plurality of circuit structures FD1 in the second direction on the second surface 1a of the substrate 1; a first isolation structure STI/9/7 disposed obliquely in a depth direction of the substrate 1 within the substrate 1, and configured to cover the first pixel transistors TG1 to prevent incident light received through the first surface 1b from flowing into the first pixel transistors TG1; and a second isolation structure STI/9/7 disposed obliquely in the depth direction of the substrate 1 within the substrate 1, and configured to cover the second pixel transistors TG1 to prevent incident light received through the first surface 1b from flowing into the second pixel transistors TG1. Regarding claim 17, see, for example, FIG. 2 wherein Hong discloses the first isolation structure STI/9/7 and the second isolation structure STI/9/7 are formed such that: a width of a photoelectric conversion region PD1/1 in which the signal carriers are formed through conversion of the incident light tapers from the first surface 1b toward the second surface 1a; and a width of a circuit region PD1/1 located under the first TG1 and second pixel transistors TG1 tapers from the first surface 1b toward the second surface 1a. Regarding claim 18, see, for example, FIG. 2 wherein Hong discloses each of the first isolation structure STI/9/7 and the second isolation structure STI/9/7 includes: a first sloped isolation structure 9/7 extending obliquely in a first diagonal direction from the first surface 1b toward the second surface 1a; and a second sloped isolation structure STI in contact with the first sloped isolation structure 9/7 on the first surface 1b and extending obliquely in a second diagonal direction symmetrical to the first diagonal direction from the first surface 1b toward the second surface 1a. INFORMATION ON HOW TO CONTACT THE USPTO Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Eugene Lee July 3, 2026 /EUGENE LEE/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Feb 05, 2024
Application Filed
Jul 09, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
87%
With Interview (+5.4%)
2y 8m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 907 resolved cases by this examiner. Grant probability derived from career allowance rate.

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