DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed 13 May 2026 have been fully considered but they are not persuasive.
Applicant argues the references fail to disclose the newly added feature, specifically the fourth dielectric layer filling the at least one recess. The examiner disagrees with applicant. Fig. 14 of Kao ‘688 clearly shows the fourth dielectric layer filling the trench and at least one recess. All claims stand rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-4, 6, 8-9, 11-14, 17, & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2021/0013143) in view of Kao et al. (US 2023/0019688).
In regards to claim 1,
Lu ‘143 discloses a capacitor structure, comprising:
a semiconductor substrate (160 – fig. 1-2 & 10; [0147]);
a stack structure comprising at least one first dielectric layer (12 – fig. 2; [0120]) and at least one second dielectric layer (11 – fig. 2; [0120]) alternately disposed on the semiconductor substrate, wherein there is a trench in the at least one first dielectric layer, the at least one second dielectric layer, and the semiconductor substrate (seen in fig. 1-2. 10, & 17), and the trench has at least one recess (seen in fig. 1-2, 10, & 17) on at least one sidewall of the at least one first dielectric layer,
a capacitor (122/124/150 – fig. 7; [0136] & [0269]) disposed on a surface of the trench; and
a third dielectric layer (123 – fig. 7; [0136] & [0269]) disposed between the capacitor and the semiconductor substrate and between the capacitor and the stack structure, wherein
the trench does not have a recess on at least one sidewall of the at least one second dielectric layer (fig. 1-2, 10, & 17),
the at least one first dielectric layer or the at least one second dielectric layer is in direct contact with the semiconductor substrate (fig. 1-2, 10, & 17), and
the at least one first dielectric layer is in direct contact with the at least one second dielectric layer (fig. 1-2, 10, & 17),
a bottom surface of the at least one first dielectric layer located on one side of the trench has the same height as a bottom surface of the at least one first dielectric layer located on another side of the trench (fig. 1-2, 10, & 17), and
a material of one of the first dielectric layer and the second dielectric layer comprises silicon nitride, silicon oxynitride, or silicon nitride carbide ([0120]). Lu ‘143 fails to disclose a fourth dielectric layer disposed on the capacitor and filled in the trench and the at least one recess.
Kao ‘688 discloses capacitor structure, comprising:
a substrate (202– fig. 9; [0050]);
a stack structure comprising at least one first dielectric layer (302L – fig. 3; [0053-0054]) and at least one second dielectric layer (304L – fig. 3; [0053-0054]) alternately disposed on the substrate, wherein there is a trench (fig. 4-5) in the at least one first dielectric layer and the at least one second dielectric layer, and the trench has at least one recess on at least one sidewall of the at least one first dielectric layer (fig. 5); and
a capacitor (fig. 9 & 14; [0066]) disposed on a surface of the trench,
a fourth dielectric layer (1402 – fig. 14; [0075]) on the capacitor and filled in the trench and at least one recess, wherein
the trench does not have a recess on at least one sidewall of the at least one second dielectric layer (fig. 4-5),
the at least one first dielectric layer or the at least one second dielectric layer is in direct contact with the substrate (fig. 3), and
the at least one first dielectric layer is in direct contact with the at least one second dielectric layer (fig. 3),
a bottom surface of the at least one first dielectric layer located on one side of the trench has the same height as a bottom surface of the at least one first dielectric layer located on another side of the trench (fig. 4), and
a material of one of the first dielectric layer and the second dielectric layer comprises silicon nitride, silicon oxynitride, or silicon nitride carbide ([0054]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a fourth dielectric as taught by Kuo ‘050 when forming the capacitor structure of Lu ‘143 as Kuo ‘050 teaches such a structure is taught to be an alternative to the electrode filling the trench and recess.
In regards to claim 3,
Lu ‘143 as modified by Kuo ‘050 further discloses wherein the trench does not have a recess on a sidewall of the semiconductor substrate (fig. 10 of Lu ‘143).
In regards to claim 4,
Lu ‘143 as modified by Kuo ‘050 further discloses wherein a sidewall of the semiconductor substrate exposed by the trench is a flat surface (fig. 10 of Lu ‘143).
In regards to claim 6,
Lu ‘143 as modified by Kuo ‘050 further discloses wherein at least one sidewall of the at least one second dielectric layer exposed by the trench is a flat surface (fig. 10 of Lu ‘143).
In regards to claim 8,
Lu ‘143 as modified by Kuo ‘050 further discloses wherein the second dielectric layer closest to the semiconductor substrate is located between the first dielectric layer closest to the semiconductor substrate and the semiconductor substrate (fig. 1-2 & 10 of Lu ‘143).
In regards to claim 9,
Lu ‘143 as modified by Kuo ‘050 further discloses wherein the capacitor is further disposed on a top surface of the stack structure (fig. 7 of Lu ‘143).
In regards to claim 11,
Lu ‘143 discloses a manufacturing method of a capacitor structure, comprising:
providing a semiconductor substrate (160 – fig. 1-2 & 10; [0147]);
forming a stack structure, wherein the stack structure comprises at least one first dielectric layer (12 – fig. 2; [0120]) and at least one second dielectric layer (11 – fig. 2; [0120]) alternately disposed on the semiconductor substrate; forming a trench in the at least one first dielectric layer, the at least one second dielectric layer, and the semiconductor substrate (seen in fig. 1-2. 10, & 17), and the trench has at least one recess (seen in fig. 1-2, 10, & 17) on at least one sidewall of the at least one first dielectric layer,
forming a capacitor (122/124/150 – fig. 7; [0136] & [0269]) on a surface of the trench,
forming a third dielectric layer (123 – fig. 7; [0136] & [0269]) between the capacitor and the semiconductor substrate and between the capacitor and the stack structure, wherein
the trench does not have a recess on at least one sidewall of the at least one second dielectric layer (fig. 1-2, 10, & 17),
the at least one first dielectric layer or the at least one second dielectric layer is in direct contact with the semiconductor substrate (fig. 1-2, 10, & 17), and
the at least one first dielectric layer is in direct contact with the at least one second dielectric layer (fig. 1-2, 10, & 17),
a bottom surface of the at least one first dielectric layer located on one side of the trench has the same height as a bottom surface of the at least one first dielectric layer located on another side of the trench (fig. 1-2, 10, & 17), and
a material of one of the first dielectric layer and the second dielectric layer comprises silicon nitride, silicon oxynitride, or silicon nitride carbide ([0120]).
Kao ‘688 discloses a manufacturing method of a capacitor structure, comprising:
providing a substrate (202– fig. 9; [0050]);
forming a stack structure, wherein the stack structure comprises at least one first dielectric layer (302L – fig. 3; [0053-0054]) and at least one second dielectric layer (304L – fig. 3; [0053-0054]) alternately disposed on the substrate;
forming a trench (fig. 4-5) in the at least one first dielectric layer and the at least one second dielectric layer, wherein the trench has at least one recess on at least one sidewall of the at least one first dielectric layer (fig. 5); and
forming a capacitor (fig. 9 & 14; [0066]) on a surface of the trench,
forming a fourth dielectric layer (1402 – fig. 14; [0075]) on the capacitor, wherein the fourth dielectric layer is filled in the trench and at least one recess (fig. 14), wherein
the trench does not have a recess on at least one sidewall of the at least one second dielectric layer (fig. 4-5),
the at least one first dielectric layer or the at least one second dielectric layer is indirect contact with the semiconductor substrate (fig. 3), and
the at least one first dielectric layer is in direct contact with the at least one second dielectric layer (fig. 3),
a bottom surface of the at least one first dielectric layer located on one side of the trench has the same height as a bottom surface of the at least one first dielectric layer located on another side of the trench (fig. 4), and
a material of one of the first dielectric layer and the second dielectric layer comprises silicon nitride, silicon oxynitride, or silicon nitride carbide ([0054]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a fourth dielectric as taught by Kuo ‘050 when forming the capacitor structure of Lu ‘143 as Kuo ‘050 teaches such a structure is taught to be an alternative to the electrode filling the trench and recess.
In regards to claim 12,
Lu ‘143 as modified by Kuo ‘050 further discloses wherein the method for forming the trench comprises: forming a patterned photoresist layer ([0207] of Lu ‘143) on the stack structure; and
using the patterned photoresist layer as a mask to remove a part of the stack structure and a part of the semiconductor substrate to form the trench ([0207] of Lu ‘143).
In regards to claim 13,
Lu ‘143 as modified by Kuo ‘050 further discloses wherein the method for removing the part of the stack structure and the part of the semiconductor substrate comprises dry etching ([0207] of Lu ‘143).
In regards to claim 14,
Lu ‘143 as modified by Kuo ‘050 further discloses further comprising: removing the patterned photoresist layer after forming the trench ([0207] of Lu ‘143).
In regards to claim 17,
Lu ‘143 as modified by Kuo ‘050 further discloses wherein the capacitor is further disposed on a top surface of the stack structure (fig. 7 of Lu ‘143).
In regards to claim 20,
Lu ‘143 as modified by Kuo ‘050 further discloses wherein the second dielectric layer closest to the semiconductor substrate is located between the first dielectric layer closest to the semiconductor substrate and the semiconductor substrate (fig. 1-2 & 10 of Lu ‘143).
Claim(s) 2 & 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu ‘143 as modified by Kao ‘688 as applied to claims 1 & 14 above, and further in view of Chi et al. (US 5,976,945).
In regards to claim 2,
Lu ‘143 as modified by Kao ‘688 fails to disclose wherein a cross-sectional contour of the at least one recess comprises a curved surface.
Chi ‘945 discloses wherein a cross-sectional contour of the at least one recess comprises a curved surface (fig. 3-4).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a recesses of Lu ‘143 as modified by Kao ‘688 to have curved surfaces as taught by Chi ‘945 to allow for an increased surface area.
In regards to claim 15,
Lu ‘143 as modified by Kao ‘688 fails to disclose explicitly wherein the method of forming the at least one recess comprises: performing an isotropic etching process on the at least one first dielectric layer to form the at least one recess.
Chi ‘945 discloses wherein the method of forming the at least one recess comprises: performing an isotropic etching process on the at least one first dielectric layer to form the at least one recess (C3:L32-35).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a recesses of Lu ‘143 as modified by Kao ‘688 using an isotropic method to obtain recesses that have curved surfaces as taught by Chi ‘945 to allow for an increased surface area.
In regards to claim 16,
Lu ‘143 as modified by Kao ‘688 and Chi ‘945 further discloses wherein the isotropic etching process comprises a dry etching process or a wet etching process (C3:L32-35 of Chi ‘945).
Claim(s) 1, 3-4, 6-7, 9, 11-14, 17, & 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2023/0063050) in view of Kao ‘688.
In regards to claim 1,
Kuo ‘050 discloses a capacitor structure, comprising:
a semiconductor substrate (8 – fig. 1; [0021]);
wherein there is a trench (fig. 2; [0023]) in the semiconductor substrate, and
a capacitor (30 – fig. 2; [0032]) disposed on a surface of the trench; and
a third dielectric layer (6 – fig. 2; [0031] of Kuo ‘050) disposed between the capacitor and the semiconductor substrate and between the capacitor and the stack structure,
a fourth dielectric layer (34 – fig. 2; [0031]) disposed on the capacitor and filled in the trench. Kuo ‘050 fails to discloses a stack structure comprising at least one first dielectric layer and at least one second dielectric layer alternately disposed on the semiconductor substrate, wherein there is a trench in the at least one first dielectric layer and the at least one second dielectric layer, and the trench has at least one recess on at least one sidewall of the at least one first dielectric layer, the fourth dielectric layer filled in the at least one recess, wherein the trench does not have a recess on at least one sidewall of the at least one second dielectric layer, the at least one first dielectric layer or the at least one second dielectric layer is in direct contact with the semiconductor substrate, and the at least one first dielectric layer is in direct contact with the at least one second dielectric layer, a bottom surface of the at least one first dielectric layer located on one side of the trench has the same height as a bottom surface of the at least one first dielectric layer located on another side of the trench, and a material of one of the first dielectric layer and the second dielectric layer comprises silicon nitride, silicon oxynitride, or silicon nitride carbide.
Kao ‘688 discloses capacitor structure, comprising:
a substrate (202– fig. 9; [0050]);
a stack structure comprising at least one first dielectric layer (302L – fig. 3; [0053-0054]) and at least one second dielectric layer (304L – fig. 3; [0053-0054]) alternately disposed on the substrate, wherein there is a trench (fig. 4-5) in the at least one first dielectric layer and the at least one second dielectric layer, and the trench has at least one recess on at least one sidewall of the at least one first dielectric layer (fig. 5); and
a capacitor (fig. 9 & 14; [0066]) disposed on a surface of the trench,
a fourth dielectric layer (1402 – fig. 14; [0075]) filled in the trench and at least one recess, wherein
the trench does not have a recess on at least one sidewall of the at least one second dielectric layer (fig. 4-5),
the at least one first dielectric layer or the at least one second dielectric layer is in direct contact with the substrate (fig. 3), and
the at least one first dielectric layer is in direct contact with the at least one second dielectric layer (fig. 3),
a bottom surface of the at least one first dielectric layer located on one side of the trench has the same height as a bottom surface of the at least one first dielectric layer located on another side of the trench (fig. 4), and
a material of one of the first dielectric layer and the second dielectric layer comprises silicon nitride, silicon oxynitride, or silicon nitride carbide ([0054]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a stack with trench and recess as taught by Kao ‘688 with the trench of Kuo ‘050 to obtain a capacitor with a greater capacitance density.
In regards to claim 3,
Kuo ‘050 as modified by Kao ‘688 further discloses wherein the trench does not have a recess on a sidewall of the semiconductor substrate (fig. 1 of Kuo ‘050).
In regards to claim 4,
Kuo ‘050 as modified by Kao ‘688 further discloses wherein a sidewall of the semiconductor substrate exposed by the trench is a flat surface (fig. 1 of Kuo ‘050).
In regards to claim 6,
Kuo ‘050 as modified by Kao ‘688 further discloses wherein at least one sidewall of the at least one second dielectric layer exposed by the trench is a flat surface (fig. 4-5 of Kao ‘688).
In regards to claim 7,
Kuo ‘050 as modified by Kao ‘688further discloses wherein the first dielectric layer closest to the semiconductor substrate is located between the second dielectric layer closest to the semiconductor substrate and the semiconductor substrate (fig. 3 of Kao ‘688).
In regards to claim 9,
Kuo ‘050 as modified by Kao ‘688 further discloses wherein the capacitor is further disposed on a top surface of the stack structure (fig. 2 of Kuo ‘050).
In regards to claim 11,
Kuo ‘050 discloses a manufacturing method of a capacitor structure, comprising:
providing a semiconductor substrate (8 – fig. 1; [0021]);
forming a trench in the semiconductor substrate (fig. 2; [0023]); and
forming a capacitor (30 – fig. 2; [0032]) on a surface of the trench,
forming a third dielectric layer (6 – fig. 2; [0031]) between the capacitor and the semiconductor substrate and between the capacitor and the stack structure,
forming a fourth dielectric layer (34 – fig. 2; [0031] of Kuo ‘050) on the capacitor, wherein the fourth dielectric layer is filled in the trench. Kuo ‘050 fails to disclose forming a stack structure, wherein the stack structure comprises at least one first dielectric layer and at least one second dielectric layer alternately disposed on the semiconductor substrate; forming a trench in the at least one first dielectric layer, wherein the fourth dielectric layer is filled in the at least one trench, the at least one second dielectric layer, wherein the trench has at least one recess on at least one sidewall of the at least one first dielectric layer; wherein the trench does not have a recess on at least one sidewall of the at least one second dielectric layer, wherein the trench does not have a recess on at least one sidewall of the at least one second dielectric layer, the at least one first dielectric layer or the at least one second dielectric layer is indirect contact with the semiconductor substrate, and the at least one first dielectric layer is in direct contact with the at least one second dielectric layer a bottom surface of the at least one first dielectric layer located on one side of the trench has the same height as a bottom surface of the at least one first dielectric layer located on another side of the trench, and a material of one of the first dielectric layer and the second dielectric layer comprises silicon nitride, silicon oxynitride, or silicon nitride carbide.
Kao ‘688 discloses a manufacturing method of a capacitor structure, comprising:
providing a substrate (202– fig. 9; [0050]);
forming a stack structure, wherein the stack structure comprises at least one first dielectric layer (302L – fig. 3; [0053-0054]) and at least one second dielectric layer (304L – fig. 3; [0053-0054]) alternately disposed on the substrate;
forming a trench (fig. 4-5) in the at least one first dielectric layer and the at least one second dielectric layer, wherein the trench has at least one recess on at least one sidewall of the at least one first dielectric layer (fig. 5); and
forming a capacitor (fig. 9 & 14; [0066]) on a surface of the trench,
forming a fourth dielectric layer (1402 – fig. 14; [0075]) filled in the trench and at least one recess, wherein
the trench does not have a recess on at least one sidewall of the at least one second dielectric layer (fig. 4-5),
the at least one first dielectric layer or the at least one second dielectric layer is indirect contact with the semiconductor substrate (fig. 3), and
the at least one first dielectric layer is in direct contact with the at least one second dielectric layer (fig. 3),
a bottom surface of the at least one first dielectric layer located on one side of the trench has the same height as a bottom surface of the at least one first dielectric layer located on another side of the trench (fig. 4), and
a material of one of the first dielectric layer and the second dielectric layer comprises silicon nitride, silicon oxynitride, or silicon nitride carbide ([0054]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a stack with trench and recess as taught by Kao ‘688 with the trench of Kuo ‘050 to obtain a capacitor with a greater capacitance density.
In regards to claim 12,
Kuo ‘050 as modified by Kao ‘688 further discloses wherein the method for forming the trench comprises: forming a patterned photoresist layer ([0056-0057] of Kao ‘688) on the stack structure; and
using the patterned photoresist layer as a mask to remove a part of the stack structure and a part of the semiconductor substrate to form the trench ([0056-0057] of Kao ‘688).
In regards to claim 13,
Kuo ‘050 as modified by Shue ‘735 further discloses wherein the method for removing the part of the stack structure and the part of the semiconductor substrate comprises dry etching ([0056-0057] of Kao ‘688).
In regards to claim 14,
Kuo ‘050 as modified by Shue ‘735 further discloses further comprising: removing the patterned photoresist layer after forming the trench ([0057] of Kao ‘688).
In regards to claim 17,
Kuo ‘050 as modified by Kao ‘688 further discloses wherein the capacitor is further formed on a top surface of the stack structure (fig. 2 of Kuo ‘050).
In regards to claim 19,
Kuo ‘050 as modified by Kao ‘688 further discloses wherein the first dielectric layer closest to the semiconductor substrate is located between the second dielectric layer closest to the semiconductor substrate and the semiconductor substrate (fig. 3 of Kao ‘688).
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David M Sinclair/Primary Examiner, Art Unit 2847
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