Prosecution Insights
Last updated: July 17, 2026
Application No. 18/433,466

MICRO LIGHT-EMITTING DIODE AND DISPLAY PANEL

Non-Final OA §102§103
Filed
Feb 06, 2024
Priority
Aug 20, 2021 — continuation of PCTCN2021113670
Examiner
PATEL, REEMA
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tianjin Sanan Optoelectronics Co., Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
996 granted / 1122 resolved
+20.8% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
34 currently pending
Career history
1156
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
61.4%
+21.4% vs TC avg
§102
10.5%
-29.5% vs TC avg
§112
11.8%
-28.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1122 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Species I (encompassing claims 1-8, 10-17, and 19-20) in the reply filed on 5/29/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (CN 101540359; published 9/23/09; references to English translation; “Wu 1”). Regarding claim 1, Wu 1 discloses a micro light-emitting diode, comprising: A semiconductor epitaxial stacked layer, comprising a first semiconductor layer (P GaP, p-AlGaInP, Fig. 1), a second semiconductor layer (n-GaP, n-AlGaInP, Fig. 1), and an active layer (MQW, Fig. 1) located between the first semiconductor layer and the second semiconductor layer ([0031]); A first electrode (P, Fig. 1) electrically connected to the first semiconductor layer ([0031]); and A second electrode (N, Fig. 1), electrically connected to the second semiconductor layer ([0031]); Wherein the second semiconductor layer (n-GaP, n-AlGaInP, Fig. 1) comprises an N-type gallium phosphide (GaP) window layer (n-GaP, Fig. 1) ([0031]), and the N-type GaP window layer is configured to play a role in current spreading ([0031]). Regarding claim 3, Wu 1 discloses a light-emitting surface is provided on a [top] side of the first semiconductor layer (P GaP, p-AlGaInP, Fig. 1), facing away from the active layer (MQW, Fig. 1), and the N-type GaP window layer (n-GaP, Fig. 1) of the second semiconductor layer is located on a (bottom) side of the active layer facing away from the light-emitting surface ([0031]). Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (CN 101540359; published 9/23/09; references to English translation; alternative interpretation “Wu 2”). Regarding claim 1, Wu 2 discloses a micro light-emitting diode, comprising: A semiconductor epitaxial stacked layer, comprising a first semiconductor layer (p-GaP, p-AlGaInP, Fig. 2), a second semiconductor layer (N GaP, n-AlGaInP, Fig. 2), and an active layer (MQW, Fig. 2) located between the first semiconductor layer and the second semiconductor layer ([0043]); A first electrode (P, Fig. 2) electrically connected to the first semiconductor layer ([0043]); and A second electrode (N, Fig. 2), electrically connected to the second semiconductor layer ([0043]); Wherein the second semiconductor layer (N GaP, n-AlGaInP, Fig. 2) comprises an N-type gallium phosphide (GaP) window layer (N GaP, Fig. 2) ([0043]), and the N-type GaP window layer is configured to play a role in current spreading ([0043]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (CN 101540359; published 9/23/09; references to English translation; alternative interpretation; “Wu 2”) as applied to claim 1 above. Regarding claim 2, Wu 2 discloses a thickness of the N-type GaP window layer (N GaP, Fig. 2) is between 4000 nm and 15,000 nm ([0043]) but does not disclose the thickness must be between 50 nm and 5000 nm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select an N-type GaP window layer thickness between 50 nm and 5000 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 4, Wu 2 discloses the N-type GaP window layer (N GaP, Fig. 2) implicitly has a doping concentration ([0043]) but does not disclose the doping concentration is in a range of 1e18 and 5e18 cm3. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select an N-type GaP window layer doping concentration to be between 1e18 and 5e18 cm3, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (CN 101540359; published 9/23/09; references to English translation; alternative interpretation; “Wu 2”) as applied to claim 1 above, and further in view of Seong et al. (U.S. 20180019378 A1; “Seong”). Regarding claims 11 and 12, Wu 2 discloses a semiconductor epitaxial stacked layer, comprising a first semiconductor layer (p-GaP, p-AlGaInP, Fig. 2), a second semiconductor layer (N GaP, n-AlGaInP, Fig. 2), and an active layer (MQW, Fig. 2) ([0043]) but does not disclose an insulation protection layer formed on a surface and a sidewall of the semiconductor epitaxial stacked layer. However, Seong discloses forming an insulation protection layer (184, Fig. 1B) comprising silicon oxide or silicon nitride on a surface and a sidewall of a semiconductor epitaxial stacked layer ([0070]). This has the advantage of protecting a surface and sidewall of the semiconductor epitaxial stacked layer. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Wu 2 with an insulation protection layer formed on a surface and a sidewall of the semiconductor epitaxial stacked layer, as taught by Seong, so as to protect a surface and sidewall of the semiconductor epitaxial stacked layer. Claim(s) 11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (CN 101540359; published 9/23/09; references to English translation; alternative interpretation; “Wu 2”) as applied to claim 1 above, and further in view of Suh et al. (U.S. 2012/0025244 A1; “Suh”). Regarding claims 11 and 13, Wu 2 discloses a semiconductor epitaxial stacked layer, comprising a first semiconductor layer (p-GaP, p-AlGaInP, Fig. 2), a second semiconductor layer (N GaP, n-AlGaInP, Fig. 2), and an active layer (MQW, Fig. 2) ([0043]) but does not disclose an insulation protection layer formed on a surface and a sidewall of the semiconductor epitaxial stacked layer. However, Suh discloses forming an insulation protection layer (37, Fig. 3) comprising a Bragg reflective layer structure on a surface and a sidewall of a semiconductor epitaxial stacked layer ([0058]). This has the advantage of protecting a surface and sidewall of the semiconductor epitaxial stacked layer. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Wu 2 with an insulation protection layer formed on a surface and a sidewall of the semiconductor epitaxial stacked layer, as taught by Suh, so as to protect a surface and sidewall of the semiconductor epitaxial stacked layer. Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (CN 101540359; published 9/23/09; references to English translation; “Wu 1”). Regarding claim 14, Wu 1 discloses a micro light-emitting diode, comprising: A semiconductor epitaxial stacked layer, comprising a first semiconductor layer (P GaP, p-AlGaInP, Fig. 1), a second semiconductor layer (n-GaP, n-AlGaInP, Fig. 1), and an active layer (MQW, Fig. 1) located between the first semiconductor layer and the second semiconductor layer ([0031]); A first electrode (P, Fig. 1) electrically connected to the first semiconductor layer ([0031]); and A second electrode (N, Fig. 1), electrically connected to the second semiconductor layer ([0031]); Wherein the second semiconductor layer (n-GaP, n-AlGaInP, Fig. 1) comprises an N-type window layer (n-GaP, Fig. 1), a material of the N-type window layer is gallium phosphide (GaP) (n-GaP, Fig. 1) ([0031]). Yet, Wu 1 does not disclose a thickness of the N-type window layer is in a range of 100-2000 nm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select an N-type window layer thickness of 100-2000 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 15, Wu 1 discloses an N-type window layer (n-GaP, Fig. 1) implicitly with a doping concentration ([0031]) but does not disclose the doping concentration is in a range of 1e18 and 5e18 cm3. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select an N-type window layer doping concentration to be between 1e18 and 5e18 cm3, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (CN 101540359; published 9/23/09; references to English translation; alternative interpretation “Wu 2”). Regarding claim 14, Wu 2 discloses a micro light-emitting diode, comprising: A semiconductor epitaxial stacked layer, comprising a first semiconductor layer (p-GaP, p-AlGaInP, Fig. 2), a second semiconductor layer (N GaP, n-AlGaInP, Fig. 2), and an active layer (MQW, Fig. 2) located between the first semiconductor layer and the second semiconductor layer ([0043]); A first electrode (P, Fig. 2) electrically connected to the first semiconductor layer ([0043]); and A second electrode (N, Fig. 2), electrically connected to the second semiconductor layer ([0043]); Wherein the second semiconductor layer (N GaP, n-AlGaInP, Fig. 2) comprises an N-type gallium phosphide (GaP) window layer (N GaP, Fig. 2) ([0043]), and the N-type GaP window layer is configured to play a role in current spreading ([0043]). Yet, Wu 2 does not disclose a thickness of the N-type window layer is in a range of 100-2000 nm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select an N-type window layer thickness of 100-2000 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 15, Wu 2 discloses an N-type window layer (N GaP, Fig. 2) implicitly with a doping concentration ([0043]) but does not disclose the doping concentration is in a range of 1e18 and 5e18 cm3. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select an N-type window layer doping concentration to be between 1e18 and 5e18 cm3, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (CN 101540359; published 9/23/09; references to English translation; alternative interpretation; “Wu 2”) as in view of Peng et al. (U.S. 2013/0328102 A1; “Peng”). Regarding claim Wu 2 discloses a light-emitting diode of claim 1 (see claim 1 rejection above) but does not disclose incorporating the light-emitting diode into a display panel. However, Peng discloses incorporating a light-emitting diode into a display panel ([0061]-[0063]). This has the advantage of forming a backlight for a display panel. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Wu 2 with the light-emitting diode incorporating into a display panel, as taught by Peng, so as to form a backlight for a display panel. Allowable Subject Matter Claims 5-8, 10, 16-17, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to REEMA PATEL whose telephone number is (571)270-1436. The examiner can normally be reached M-F, 8am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /REEMA PATEL/Primary Examiner, Art Unit 2812 6/25/2026
Read full office action

Prosecution Timeline

Feb 06, 2024
Application Filed
Jun 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
95%
With Interview (+6.4%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1122 resolved cases by this examiner. Grant probability derived from career allowance rate.

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