CTNF 18/433,741 CTNF 102178 DETAILED ACTION This office action is in response to application filed on February 2 nd , 2024 in which claims 1-20 are pending in the application. Claims 1, 8, and 14 are in independent form. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-27 AIA Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. GR20230100165 , filed on February 24th, 2023 . Information Disclosure Statement The information disclosure statement (IDS) submitted on April 30th, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification 07-29 AIA The disclosure is objected to because of the following informalities: Paragraph [0053] which states "herein231". Paragraph [304] which states "ap-plications" . Appropriate correction is required. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1 – 20 are rejected under 35 USC 101 as being directed to an abstract idea without significantly more. Step 1: Claims 1-7 are directed to a computer program product and therefore a manufacture which is one of the statutory categories of inventions. Claims 8-13 are directed to a system and therefore is a machine which is one of the statutory categories of inventions. Claims 14-20 are directed to a method (series of steps) and therefore is a process which is one of the statutory categories of inventions. Step 2A, Prong 1: Claims 1, 8, and 14 recite the limitations “perform… an application programming interface” and “select, from a group of threads, one or more threads” and “one or more threads to be modified” are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the functions through observation, evaluation, judgement, and/or opinion, with or without the aid of pen and paper. Thus, these limitations recite and fall within the “Mental Processes” grouping of abstract ideas under Prong 1. Step 2A, Prong 2: This judicial exception is not integrated into a practical application. The processors and APIs in these steps are recited at a high-level of generality (i.e., as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). The claim is directed to an abstract idea. Step 2B: This judicial exception is not integrated into a practical application. The processors and APIs in these steps are recited at a high-level of generality (i.e., as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). The claim is directed to an abstract idea. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The limitations are recognized by the courts as well-understood, routine, and conventional activities when they are merely claimed in a merely generic manner. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of the “processor(s)” are merely a generic computer or generic computer components to apply the judicial exception which cannot provide an inventive concept. Accordingly, the claim does not appear to be patent eligible under 35 USC 101. Dependent Claim 2 recites the limitation “one or more threads are to be modified to include a set of instructions to be performed by the one or more threads.” This limitation is a mental process because it describes acts of observation, evaluation, judgement, selection, or opinion that can be performed in the human mind. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). Dependent Claim 3 recites the limitation “one or more threads are to be performed by a single core of a streaming multiprocessor (SM).” This limitation is a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (see MPEP 2106.05(g)). Dependent Claim 4 recites the limitation “one or more threads are to be modified to cause one or more other processors to perform an invocable object.” This limitation is a mental process because it describes acts of observation, evaluation, judgement, selection, or opinion that can be performed in the human mind. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). Dependent Claim 5 recites the limitation “one or more threads are to be selected based, at least in part, on an instruction to cause the processor to select the one or more threads.” This limitation is a mental process because it describes acts of observation, evaluation, judgement, selection, or opinion that can be performed in the human mind. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). Dependent Claim 6 recites the limitation “one or more threads are to be modified to include and invocable object and at least one of the one or more threads are to be performed by an other processor.” This limitation is a mental process because it describes acts of observation, evaluation, judgement, selection, or opinion that can be performed in the human mind. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). Dependent Claim 7 recites the limitation “the group of threads is to be performed in parallel by a streaming multiprocessor (SM).” This limitation is a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (see MPEP 2106.05(g)). Dependent Claim 9 recites the limitation “one or more threads are to be modified based, at least in part, on a set of instructions to be performed by the one or more threads by a single core of another processor.” This limitation is a mental process because it describes acts of observation, evaluation, judgement, selection, or opinion that can be performed in the human mind. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). Dependent Claim 10 recites the limitation “the group of threads is to be performed in parallel by a streaming multiprocessor (SM) and the one or more threads are to be selected based, at least in part, on an availability of the one or more threads to be performed by at least one core of the SM.” This limitation is a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (see MPEP 2106.05(g)). Dependent Claim 11 recites the limitation “one or more threads are to be selected from a group of threads based, at least in part, on an instruction performed by the one or more processors to select the one or more threads.” This limitation is a mental process because it describes acts of observation, evaluation, judgement, selection, or opinion that can be performed in the human mind. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). Dependent Claim 12 recites the limitation “one or more threads are to be modified to cause one or more invocable objects to be performed.” This limitation is a mental process because it describes acts of observation, evaluation, judgement, selection, or opinion that can be performed in the human mind. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). Dependent Claim 13 recites the limitation “one or more threads are to be performed by at least one core of a streaming multiprocessor (SM).” This limitation is a mental process because it describes acts of observation, evaluation, judgement, selection, or opinion that can be performed in the human mind. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). Dependent Claim 15 recites the limitation “selecting the one or more threads based, at least in part, on an instruction performed by a processor performing the API.” This limitation is a mental process because it describes acts of observation, evaluation, judgement, selection, or opinion that can be performed in the human mind. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). Dependent Claim 16 recites the limitation “modifying the one or more threads to cause a single core of a processor to perform an invocable object.” This limitation is a mental process because it describes acts of observation, evaluation, judgement, selection, or opinion that can be performed in the human mind. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). Dependent Claim 17 recites the limitation “the group of threads is to be performed in parallel by a streaming multiprocessor (SM).” This limitation is a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (see MPEP 2106.05(g)). Dependent Claim 18 recites the limitation “modifying the one or more threads to include a set of instructions to be performed by a single core of a processor.” This limitation is a mental process because it describes acts of observation, evaluation, judgement, selection, or opinion that can be performed in the human mind. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). Dependent Claim 19 recites the limitation “modifying the one or more threads by causing the one or more threads to cause one or more processors to perform an invocable object.” This limitation is a mental process because it describes acts of observation, evaluation, judgement, selection, or opinion that can be performed in the human mind. These additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). Dependent Claim 20 recites the limitation “performing the one or more threads by a single core of a streaming multiprocessor (SM).” This limitation is a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (see MPEP 2106.05(g)). Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-20 are rejected under 35 U.S.C. 102( a)(1) and 102(a)(2 ) as being anticipated by Edwards (U.S. Patent No. 20210294673), hereinafter Edwards . As per claim 1, Edwards teaches a processor comprising: one or more circuits to perform an application programming interface (API) to select, from a group of threads, one or more threads to be modified. [ Paragraph [0064], a single thread 308 is selected from a thread group 302 to perform a prologue 332 through an application programming interface (API); Paragraph [0057], epilogue 218 is performed once a last thread of a thread group 204, 206, 208 has completed modifying one or more shared data values; Paragraph [0047], a central processing unit (CPU) or graphics processing unit (GPU) used to facilitate data storage and sharing between multiple threads 106, 108, 110, 112 ]. As per claim 2, Edwards teaches the processor of claim 1, wherein the one or more threads are to be modified to include a set of instructions to be performed by the one or more threads. [ Paragraph [0055], In at least one embodiment, a body 214 is performed after a synchronization 222. In at last one embodiment, a body 214 is a set of instructions that, when executed, perform parallel operations on shared data by one or more threads 204, 206, 208. ]. As per claim 3, Edwards teaches the processor of claim 1, wherein the one or more threads are to be performed by a single core of a streaming multiprocessor (SM). [ Paragraph [0093], In at least one embodiment, each of one or more processor cores 707 is configured to process a specific instruction set 709; Paragraph [0227], In at least one embodiment, scheduler unit 2404 receives tasks from a work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 2400. In at least one embodiment, scheduler unit 2404 schedules thread blocks for execution as warps of parallel threads, wherein each thread block is allocated at least one warp. ]. As per claim 4, Edwards teaches the processor of claim 1, wherein the one or more threads are to be modified to cause one or more other processors to perform an invocable object. In view of the specification, paragraph 0092, under BRI, the examiner considers an invocable object to be a(n set of) instruction(s), therefore [ Paragraph [0057], epilogue 218 is performed once a last thread of a thread group 204, 206, 208 has completed modifying one or more shared data values; Paragraph [0047], a central processing unit (CPU) or graphics processing unit (GPU) used to facilitate data storage and sharing between multiple threads 106, 108, 110, 112; Paragraph [0065], In at least one embodiment, threads 304, 306, 308, 310 perform instructions 312, 314, 316, 318; Paragraph [0203], Graphics SoC interface 2137 provides an interface between graphics core 2100 and other processor cores within an SoC integrated circuit. In at least one embodiment, graphics microcontroller 2138 is a programmable sub-processor that is configurable to manage various functions of graphics processor 2100, including thread dispatch, scheduling, and pre-emption. ]. As per claim 5, Edwards teaches the processor of claim 1, wherein the one or more threads are to be selected based, at least in part, on an instruction to cause the processor to select the one or more threads. [ Paragraph [0064], In at least one embodiment, a prologue 332 is performed by a single thread 308 selected from a thread group 302. In at least one embodiment, a single thread 308 is selected from a thread group 302 to perform a prologue 332 through an application programming interface (API) to facilitate parallel computing, such as CUDA or other APIs described herein. In at least one embodiment, a single thread 308 is selected from a thread group 302 by a thread scheduler based on instructions 312, 314, 316, 318 contained in each thread 304, 306, 308, 310. In at least one embodiment, a single thread 308 is selected from a thread group 302 by other threads 304, 306, 310 in a thread group 302 containing said selected thread 308. ]. As per claim 6, the claim is rejected using the same rationale as noted above for claim 4. As per claim 7, Edwards teaches the processor of claim 1, wherein the group of threads is to be performed in parallel by a streaming multiprocessor (SM). [ Paragraph [0227], In at least one embodiment, scheduler unit 2404 receives tasks from a work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 2400. In at least one embodiment, scheduler unit 2404 schedules thread blocks for execution as warps of parallel threads, wherein each thread block is allocated at least one warp. ]. As per claim 8, the claim is rejected using the same rationale as noted above for claim 1. Edwards further teaches a system comprising: one or more processors, this is still covered by prior art noted in claim 1. As per claim 9, Edwards teaches the system of claim 8, wherein the one or more threads are to be modified based, at least in part, on a set of instructions to be performed by the one or more threads by a single core of another processor. [ Paragraph [0057], epilogue 218 is performed once a last thread of a thread group 204, 206, 208 has completed modifying one or more shared data values; Paragraph [0203], Graphics SoC interface 2137 provides an interface between graphics core 2100 and other processor cores within an SoC integrated circuit. In at least one embodiment, graphics microcontroller 2138 is a programmable sub-processor that is configurable to manage various functions of graphics processor 2100, including thread dispatch, scheduling, and pre-emption; Paragraph [0093], In at least one embodiment, each of one or more processor cores 707 is configured to process a specific instruction set 709 ]. As per claim 10, the claim is rejected using the same rationale as noted above for claim 7. Edwards further teaches one or more threads are to be selected based, at least in part, on an availability of the one or more threads to be performed by at least one core of the SM. [ Paragraph [0227], scheduler unit 2404 manages a plurality of different thread blocks, allocating warps to different thread blocks and then dispatching instructions from a plurality of different cooperative groups to various functional units (e.g., processing cores 2410, SFUs 2412, and LSUs 2414) during each clock cycle.; Paragraph [0093], In at least one embodiment, each of one or more processor cores 707 is configured to process a specific instruction set 709 ]. As per claim 11, the claim is rejected using the same rationale as noted above for claim 1. As per claim 12, the claim is rejected using the same rationale as noted above for claim 4. As per claim 13, the claim is rejected using the same rationale as noted above for claim 3. As per claim 14, the claim is rejected using the same rationale as noted above for claim 1. As per claim 15, the claim is rejected using the same rationale as noted above for claim 1. As per claim 16, the claim is rejected using the same rationale as noted above for claim 4. Edwards further teaches that the one or more threads causes a single core of a processor to perform an invocable object. [ Paragraph [0093], In at least one embodiment, each of one or more processor cores 707 is configured to process a specific instruction set 709. ]. As per claim 17, the claim is rejected using the same rationale as noted above for claim 7. As per claim 18, the claim is rejected using the same rationale as noted above for claim 2. Edwards further teaches the set of instructions to be performed by a single core of a processor. [ Paragraph [0093], In at least one embodiment, each of one or more processor cores 707 is configured to process a specific instruction set 709. ]. As per claim 19, the claim is rejected using the same rationale as noted above for claim 4. As per claim 20, the claim is rejected using the same rationale as noted above for claim 3 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Brewer (U.S. Patent No. 20190340023) teaches a self-scheduling processor. The processor includes functionality to execute received instructions, select cores to execute from, and send other processors instructions to execute. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAZAN A ALSHOROOGI whose telephone number is (571)270-0893. The examiner can normally be reached Tuesday - Friday 7am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571) 272-4215. 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May 22, 2026 /YAZAN ABDELNASER ALSHOROOGI/Examiner, Art Unit 2198 /TUAN C DAO/Primary Examiner, Art Unit 2198 Application/Control Number: 18/433,741 Page 2 Art Unit: 2198 Application/Control Number: 18/433,741 Page 3 Art Unit: 2198 Application/Control Number: 18/433,741 Page 4 Art Unit: 2198 Application/Control Number: 18/433,741 Page 5 Art Unit: 2198 Application/Control Number: 18/433,741 Page 6 Art Unit: 2198 Application/Control Number: 18/433,741 Page 7 Art Unit: 2198 Application/Control Number: 18/433,741 Page 8 Art Unit: 2198 Application/Control Number: 18/433,741 Page 9 Art Unit: 2198 Application/Control Number: 18/433,741 Page 11 Art Unit: 2198
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