DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11 and 16 have been considered but are moot because the new ground of rejection does not rely on how any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argue son page 10 of the REMARKS, “Respectfully, Applicant notes that Chung's element 304, which the Examiner equates to the claimed second PCB, is actually a vertical package section of an IC package, not a PCB. As set forth in Chung: "The electrical assembly includes an integrated circuit 302 (IC) and an IC package consisting of a vertical package section 304 and a horizontal package section 306." (Chung, 0027, emphasis in original.) Chung, at paragraph 0033, further distinguishes vertical package section 304 from a printed circuit board. Specifically: "the vertical section 304 serves to convert the pitch, along the Y-axis, from the bond pad pitch of IC 302 to a larger pitch, such as the desired pitch for mating the package's bottom surface connections with a next level of interconnect (e.g., an interposer, socket, printed circuit board or other substrate)." (Chung, 0033, emphasis added.) In other words, Chung distinguishes between a vertical package section and a printed circuit board”. The Office respectfully disagrees. Chung states at [0030] “standard printed circuit board materials, such materials are used to construct vertical section 304”. [0037] states “Horizontal section 306 includes multiple layers of conductive materials separated by multiple layers of dielectric materials”. [0065-0076] discuss the process of making the invention of Chung and how “Generally, the fabrication process begins by providing a substrate, which can be formed from organic PC board materials, such as an epoxy material, in one embodiment. For example, standard PC board materials such as FR-4 epoxy-glass, polymide-glass, benzocyclobutene, Teflon, other epoxy resins, injection molded plastic or the like could be used in various embodiments. In alternate embodiments, the substrate could consist of inorganic PC board materials, such as ceramic, for example”. As seen by Chung, the vertical section and the horizontal sections are formed from PCB materials and are thus circuit board structures. Furthermore a printed circuit board is generally defined as comprising insulating material with conductive pathways that connect electronic components. As seen by Fig 3-5, Chung is teaching of first and second printed circuit boards as the structures 304 and 306 comprise insulating material with conductive pathways that connect electronic components.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3 – 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2003/0003705 A1) in view of Ooyabu (US 7,482,800 B2).
Regarding Claim 1, Chung (US 2003/0003705 A1) discloses an electronic product (Fig 3-5), comprising: a first printed circuit board (PCB) (306; [0030,0032,0037,0042,0065-0076]; insulating material with conductive pathways that connect electronic components) having one or more electronic components (310) disposed on a first major surface (upper surface of 306) thereof, the first PCB (306) having a first size (see Fig 5 showing a dimension of size of 306 in the left-right direction; note that the claim has not claimed a structural datum for establishing the claimed size; [0044]); and a second PCB (304; [0030,0032,0037,0042,0065-0076]; insulating material with conductive pathways that connect electronic components), the second PCB (304) having a second size (see Fig 5 showing a dimension of size of 304 in the up-down direction; note that the claim has not claimed a structural datum for establishing the claimed size; [0044]), and further having one or more capacitors (308; [0034]) disposed thereon, wherein the first edge (lower surface of 304 in Fig 5) of the second PCB (304) are soldered ([0049]) to the first major surface of the first PCB (306), wherein the second size is smaller than the first size (see Fig 5 showing 304 having a smaller size in the left-right direction than 306; [0044]), and wherein the second PCB (304) is nominally orthogonal (see Fig 5 showing 304 is nominally orthogonal to 306; [0029]) to the first printed circuit board (306).
Chung does not disclose a second PCB having castellated vias on a first edge thereof, wherein the castellated vias on the first edge of the second PCB are soldered to the first major surface of the first PCB.
Ooyabu (US 7,482,800 B2) teaches of an electronic product (Fig 1-8), comprising: a first printed circuit board (PCB) (21; Column 4, lines 18-34) having one or more electronic components (25; Column 9, lines 24-32) disposed on a first major surface (upper surface of 21) thereof, the first PCB (21) having a first size (see Fig 8 showing a dimension of size of 21 in the left-right direction; note that the claim has not claimed a structural datum for establishing the claimed size); and a second PCB (1; Column 4, lines 18-34) having castellated vias (at 10) on a first edge (lower edge of 1 as seen in Fig 2) thereof, the second PCB (1) having a second size (see Fig 8 showing a dimension of size of 1 in the up-down direction; note that the claim has not claimed a structural datum for establishing the claimed size), wherein the castellated vias (at 10) on the first edge of the second PCB (1) are soldered (29) to the first major surface (upper surface of 21 as seen in Fig 7) of the first PCB (21), wherein the second size is smaller than the first size (see Fig 8 showing height of 1 is smaller in size than width of 21), and wherein the second PCB (1) is nominally orthogonal (see Fig 1-8 showing 1 is nominally orthogonal to 21; Abstract) to the first printed circuit board (21).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the product as disclosed by Chung, wherein the second PCB having castellated vias on a first edge thereof, wherein the castellated vias on the first edge of the second PCB are soldered to the first major surface of the first PCB as taught by Ooyabu, in order to allow a reduction in size, allow a precise connection, provide precise positioning and providing a simple, precise connection structure (Ooyabu, Abstract, Column 2, lines 13-59, Column 8, lines 1-14).
Regarding Claim 3, Chung further discloses the electronic product (Fig 8-9) of claim 1, wherein the one or more capacitors (308) are attached to a first side (left side of Fig 4-5) of the second PCB (304).
Regarding Claim 4, Chung further discloses the electronic product (Fig 3-5), wherein at least a first one of one or more capacitors (308; [0048]) is attached to a first side (e.g. right side of 304 in Fig 5) of a second PCB (304; [0042]), and at least a second one of the one or more capacitors (308) is attached to a second, opposite side (e.g. left side of 304 in Fig 5) of the second PCB (304).
Regarding Claim 5, Chung further discloses the electronic product (Fig 3-5) of claim 4, wherein the first one of the one or more capacitors (308) and the second one of the one or more capacitors (308) are coupled to electrically conductive material ([0036,0049]) disposed on or in the first PCB (306;[0042]).
Regarding Claim 6, Chung further discloses the electronic product (Fig 3-5), wherein a first one of one or more capacitors (308) is a two terminal device (see Fig 5; [0034,0048]) having a first terminal (not labeled; interfacing with right side 512; [0045-0050]) coupled to a first power plane (right side 540; [0045-0053]) on a first PCB (306), and having a second terminal (not labeled; interfacing with right side 514; [0045-0050]) coupled to a first ground plane (right side 542; [0045-0053]) on the first PCB.
Regarding Claim 7, Chung further discloses the electronic product (Fig 3-5) of claim 6, wherein a second one of the one or more capacitors (308 on the other side of 304) is a two terminal device (see Fig 5; [0034,0048]) having a first terminal (not labeled; interfacing with left side 512; [0045-0050]) coupled to a second power plane (left side 540; [0045-0053]) on the first PCB, and having a second terminal (not labeled; interfacing with left side 514; [0045-0050]) coupled to a second ground plane (left side 542; [0045-0053]) on the first PCB.
Claim(s) 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2003/0003705 A1) in view of Ooyabu (US 7,482,800 B2) as applied to claim 1 above, and further in view of Kledzik (US 2003/0165051 A1).
Regarding Claim 2, Chung in view of Ooyabu teaches the limitations of the preceding claim.
Chung further discloses the electronic product (Fig 3-5) of claim 1, wherein at least one surface-mount capacitor (308) is disposed on the second PCB (304).
Chung does not disclose the electronic product of claim 1, wherein the one or more electronic components comprise at least one integrated circuit.
Kledzik (US 2003/0165051 A1) teaches of an electronic product (Fig 1-3), wherein one or more electronic components (52) comprise at least one integrated circuit ([0048]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the product as taught by Chung in view of Ooyabu, wherein the one or more electronic components comprise at least one integrated circuit as taught by Kledzik, in order to allow for chip operations, to operate a computer, to meet demands of increased memory, meet demands of faster computers, increase circuit density, and increase operating speed (Kledzik, [0003-0008,0048,0076]).
Regarding Claim 10, Chung in view of Ooyabu teaches the limitations of the preceding claim.
Chung does not disclose the electronic product of claim 1, wherein a first one of the one or more electronic components is an integrated circuit electrically coupled to the first PCB by a ball grid array package.
Kledzik (US 2003/0165051 A1) teaches of an electronic product, wherein a first one of one or more electronic components (51,52) is an integrated circuit ([0048]) electrically coupled to a first PCB (43) by a ball grid array package ([0046-0048]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the product as taught by Chung in view of Ooyabu, wherein a first one of the one or more electronic components is an integrated circuit electrically coupled to the first PCB by a ball grid array package as taught by Kledzik, in order to allow for chip operations, to operate a computer, to meet demands of increased memory, meet demands of faster computers, increase circuit density, eliminate leads, decrease signal distance, and increase operating speed (Kledzik, [0003-0008,0048,0076]).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2003/0003705 A1) in view of Ooyabu (US 7,482,800 B2) as applied to claim 1 above, and further in view of Hattori (US 2017/0339792 A1).
Regarding Claim 8, Chung in view of Ooyabu teaches the limitations of the preceding claim.
Chung does not explicitly disclose the electronic product of claim 1, wherein at least two of the one or more capacitors are coupled in parallel.
Hattori (US 2017/0339792 A1) teaches of an electronic product (Fig 10-13), wherein at least two of one or more capacitors (10A,10B) are coupled in parallel ([0156]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the product as taught by Chung in view of Ooyabu, wherein at least two of the one or more capacitors are coupled in parallel as taught by Hattori, in order to allow connection to a same power line and allow coupling to a same node (Hattori, [0156]). Please note that in the instant application, page 2, [0011], Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2003/0003705 A1) in view of Ooyabu (US 7,482,800 B2) as applied to claim 1 above, and further in view of Shimada (US 2012/0081861 A1).
Regarding Claim 9, Chung in view of Ooyabu teaches the limitations of the preceding claim.
Chung does not disclose the electronic product of claim 1, wherein a first one of the one or more capacitors has a first capacitance, a second one of the one or more capacitors has a second capacitance, and the first capacitance is different from the second capacitance.
Shimada (US 20120081861 A1) teaches of an electronic (Fig 1-2), wherein a first one (16) of one or more capacitors (16,17) has a first capacitance ([0052]), a second one of the one or more capacitors has a second capacitance ([0053]), and the first capacitance is different ([0052-0053]) from the second capacitance.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the product as taught by Chung in view of Ooyabu, wherein a first one of the one or more capacitors has a first capacitance, a second one of the one or more capacitors has a second capacitance, and the first capacitance is different from the second capacitance as taught by Shimada, in order to provide voltage conversion and stabilization (Shimada, [0002-0022, 0052-0055]).
Claim(s) 11, 12, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2003/0003705 A1) in view of Gokan (US 8,093,505 B2), Kledzik (US 2003/0165051 A1) and Ooyabu (US 7,482,800 B2).
Regarding Claim 11, Chung discloses an electronic product (Fig 3-5), comprising: a first substrate (306; [0030,0032,0037,0042,0065-0076]; insulating material with conductive pathways that connect electronic components), and further having a first power supply plane (right side 540; [0045-0053]) and a second power supply plane (left side 540; [0045-0053]), the first substrate (306) having a first size (see Fig 5 showing a dimension of size of 306 in the left-right direction; note that the claim has not claimed a structural datum for establishing the claimed size; [0044]); and a second substrate (304; [0030,0032,0037,0042,0065-0076]; insulating material with conductive pathways that connect electronic components) having a plurality of capacitors (308; [0034]) coupled thereto, the second substrate (304) having a second size (see Fig 5 showing a dimension of size of 304 in the up-down direction; note that the claim has not claimed a structural datum for establishing the claimed size; [0044]) that is smaller than the first size, wherein the second substrate (304) is soldered ([0049]) to the first substrate (306) such that each capacitor (308) of the plurality of capacitors is coupled to the first power supply plane (540) and the second power supply plane (540), and wherein the second substrate and the first substrate are nominally orthogonal (see Fig 5 showing 304 is nominally orthogonal to 306; [0029]) to each other.
Chung does not disclose having a plurality of integrated circuits coupled thereto and further having a plurality of castellated vias disposed at an edge thereof, and the plurality of castellated vias are vertically adjacent to the first substrate.
Gokan teaches of an electronic product (Fig 8-9), comprising: a first substrate (101,102) having a plurality of integrated circuits (105,105) coupled thereto; and a second substrate (10d,10b) having a plurality of capacitors (111,112) coupled thereto, and further having a plurality of castellated vias (108; Column 5, lines 19-32) disposed at an edge (end edges of 10d,10b) thereof, wherein the second substrate (10d,10b) is coupled to the first substrate (101,102) such that each capacitor (111,112) of the plurality of capacitors is coupled, and wherein the second substrate (10d,10b) and the first substrate (101,102) are nominally orthogonal (see Fig 8-9) to each other, and the plurality of castellated vias (108) are vertically adjacent (see Fig 8-9) to the first substrate (101,102).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the product as disclosed by Chung, having a plurality of integrated circuits coupled thereto as taught by Gokan, in order to allow for chip operations, to operate a computer, to meet demands of increased memory, meet demands of faster computers, increase circuit density, eliminate leads, decrease signal distance, and increase operating speed (Kledzik, [0003-0008,0048,0076]).
Ooyabu (US 7,482,800 B2) teaches of an electronic product (Fig 1-8), comprising: a first substrate (21; Column 4, lines 18-34) having one or more electronic components (25; Column 9, lines 24-32) disposed on a first major surface (upper surface of 21) thereof, the first substrate (21) having a first size (see Fig 8 showing a dimension of size of 21 in the left-right direction; note that the claim has not claimed a structural datum for establishing the claimed size); and a second substrate (1; Column 4, lines 18-34) having a plurality of castellated vias (at 10) disposed at an edge lower edge of 1 as seen in Fig 2) thereof, and the plurality of castellated vias (10) are vertically adjacent to the first substrate (21), the second substrate (1) having a second size (see Fig 8 showing a dimension of size of 1 in the up-down direction; note that the claim has not claimed a structural datum for establishing the claimed size), wherein the castellated vias (at 10) on the first edge of the second substrate (1) are soldered (29) to the first major surface (upper surface of 21 as seen in Fig 7) of the first substrate (21), wherein the second size is smaller than the first size (see Fig 8 showing height of 1 is smaller in size than width of 21), and wherein the second substrate (1) is nominally orthogonal (see Fig 1-8 showing 1 is nominally orthogonal to 21; Abstract) to the first substrate (21).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the product as taught by Chung in view of Gokan and Kledzik, further having a plurality of castellated vias disposed at an edge thereof, and the plurality of castellated vias are vertically adjacent to the first substrate as taught by Ooyabu, in order to allow a reduction in size, allow a precise connection, provide precise positioning and providing a simple, precise connection structure (Ooyabu, Abstract, Column 2, lines 13-59, Column 8, lines 1-14).
Regarding Claim 12, Chung in view of Gokan, Kledzik and Ooyabu teaches the limitations of the preceding claim.
Chung further discloses the electronic product (Fig 3-5) of claim 1, wherein the plurality of capacitors (308) are surface-mount capacitors (see Fig 5).
Chung does not explicitly disclose the electronic product of claim 11, wherein at least one of the plurality of integrated circuits includes a ball grid array package.
Kledzik (US 2003/0165051 A1) teaches of an electronic product, wherein at least one of a plurality of integrated circuits (51,52) includes a ball grid array package ([0046-0048]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the product as taught by Chung in view of Gokan, Kledzik and Ooyabu, wherein at least one of the plurality of integrated circuits includes a ball grid array package as taught by Kledzik, in order to allow for chip operations, to operate a computer, to meet demands of increased memory, meet demands of faster computers, increase circuit density, eliminate leads, decrease signal distance, and increase operating speed (Kledzik, [0003-0008,0048,0076]).
Regarding Claim 14, Chung in view of Gokan, Kledzik and Ooyabu teaches the limitations of the preceding claim.
Chung further discloses of an electronic product (Fig 3-5), wherein a first portion of the plurality of capacitors (308) is disposed on a first side (left side of 304) of the second substrate (304), and a second portion of the plurality of capacitors (308) is disposed on a second side (right side of 304) of the second substrate (304).
Regarding Claim 15, Chung in view of Gokan, Kledzik and Ooyabu teaches the limitations of the preceding claim.
Chung further discloses the electronic product (Fig 8-9) of claim 11, wherein the first substrate (306) comprises a multi-layer printed circuit board ([0030,0032,0037,0042,0065-0076]; insulating material with conductive pathways that connect electronic components), and the plurality of capacitors (308) are surface-mount capacitors (see Fig 5).
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2003/0003705 A1) in view of Gokan (US 8,093,505 B2), Kledzik (US 2003/0165051 A1) and Ooyabu (US 7,482,800 B2) as applied to claim 11 above, and further in view of Shimada (US 2012/0081861 A1).
Regarding Claim 13, Chung in view of Gokan, Kledzik and Ooyabu teaches the limitations of the preceding claim.
Chung does not disclose the electronic product of claim 11, wherein a first capacitor of the plurality of capacitors has a first nominal capacitance, a second capacitor of the plurality of capacitors has a second nominal capacitance, and the first nominal capacitance is greater than the second nominal capacitance.
Shimada teaches of an electronic product (Fig 1-2), wherein a first capacitor (17) of a plurality of capacitors (16,17) has a first nominal capacitance ([0052-0053]), a second capacitor (16) of the plurality of capacitors has a second nominal capacitance ([0052-0053]), and the first nominal capacitance is greater than the second nominal capacitance ([0052-0053]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the product as taught by Chung in view of Gokan, Kledzik and Ooyabu, wherein a first capacitor of the plurality of capacitors has a first nominal capacitance, a second capacitor of the plurality of capacitors has a second nominal capacitance, and the first nominal capacitance is greater than the second nominal capacitance as taught by Shimada, in order to provide voltage conversion and stabilization (Shimada, [0002-0022, 0052-0055]).
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2003/0003705 A1) in view of Kledzik (US 2003/0165051 A1) and Ooyabu (US 7,482,800 B2).
Regarding Claim 16, Chung discloses an apparatus (Fig 3-5), comprising: a first printed circuit board (PCB) (306; [0030,0032,0037,0042,0065-0076]; insulating material with conductive pathways that connect electronic components) having a plurality of components (310) attached thereto, the first PCB (306) having a first size (see Fig 5 showing a dimension of size of 306 in the left-right direction; note that the claim has not claimed a structural datum for establishing the claimed size; [0044]); and a second PCB (304; [0030,0032,0037,0042,0065-0076]; insulating material with conductive pathways that connect electronic components) having a plurality of surface-mount capacitors (308) attached thereto, the second PCB (304) having a second size (see Fig 5 showing a dimension of size of 304 in the up-down direction; note that the claim has not claimed a structural datum for establishing the claimed size; [0044]) that is smaller than the first size, wherein the first PCB (306) and the second PCB (304) are attached to each other such that the first PCB and the second PCB are nominally orthogonal (see Fig 5 showing 304 is nominally orthogonal to 306; [0029]).
Chung does not disclose at least one of the components being attached to the first PCB by a ball grid array package and further having a first edge comprising a plurality of castellated vias and the plurality of castellated vias are soldered to and vertically adjacent to the first PCB.
Kledzik (US 2003/0165051 A1) teaches of an apparatus (Fig 1-3), wherein at least one of components (51,52) being attached to a first PCB (43) by a ball grid array package ([0046-0048]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as disclosed by Chung, wherein at least one of the components being attached to the first PCB by a ball grid array package as taught by Kledzik, in order to allow for chip operations, to operate a computer, to meet demands of increased memory, meet demands of faster computers, increase circuit density, eliminate leads, decrease signal distance, and increase operating speed (Kledzik, [0003-0008,0048,0076]).
Ooyabu (US 7,482,800 B2) teaches of an electronic product (Fig 1-8), comprising: a first PCB (21; Column 4, lines 18-34) having one or more electronic components (25; Column 9, lines 24-32) disposed on a first major surface (upper surface of 21) thereof, the first PCB (21) having a first size (see Fig 8 showing a dimension of size of 21 in the left-right direction; note that the claim has not claimed a structural datum for establishing the claimed size); and a second PCB (1; Column 4, lines 18-34) having a plurality of castellated vias (at 10) disposed at an edge lower edge of 1 as seen in Fig 2) thereof, and the plurality of castellated vias (10) are vertically adjacent to the first PCB (21), the second PCB (1) having a second size (see Fig 8 showing a dimension of size of 1 in the up-down direction; note that the claim has not claimed a structural datum for establishing the claimed size), wherein the castellated vias (at 10) on the first edge of the second PCB (1) are soldered (29) to the first major surface (upper surface of 21 as seen in Fig 7) of the first PCB (21), wherein the second size is smaller than the first size (see Fig 8 showing height of 1 is smaller in size than width of 21), and wherein the second PCB (1) is nominally orthogonal (see Fig 1-8 showing 1 is nominally orthogonal to 21; Abstract) to the first PCB (21).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the product as taught by Chung in view of Kledzik, further having a first edge comprising a plurality of castellated vias and the plurality of castellated vias are soldered to and vertically adjacent to the first PCB as taught by Ooyabu, in order to allow a reduction in size, allow a precise connection, provide precise positioning and providing a simple, precise connection structure (Ooyabu, Abstract, Column 2, lines 13-59, Column 8, lines 1-14).
Regarding Claim 17, Chung in view of Kledzik and Ooyabu teaches the limitations of the preceding claim.
Chung further discloses the electronic product (Fig 3-5) of claim 16, wherein the plurality of surface-mount capacitors (308) are attached to a first side (side of 304 in Fig 5) of the second PCB (304).
Regarding Claim 18, Chung in view of Kledzik and Ooyabu teaches the limitations of the preceding claim.
Chung further discloses the apparatus (Fig 3-5) of claim 16, wherein the second PCB (304) is a two-sided PCB, a first portion of the plurality of surface-mount capacitors (308 on left side of Fig 4) are attached to a first side of the two-sided PCB, and a second portion of the plurality of surface-mount capacitors (308 on right side of Fig 4) are attached to a second side of the second PCB.
Claim(s) 19 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2003/0003705 A1) in view of Kledzik (US 2003/0165051 A1) and Ooyabu (US 7,482,800 B2) as applied to claim 16 above, and further in view of Shimada (US 2012/0081861 A1).
Regarding Claim 19, Chung in view of Kledzik and Ooyabu teaches the limitations of the preceding claim.
Chung does not disclose the apparatus of claim 16, wherein a first portion of the plurality of surface-mount capacitors have a first nominal capacitance.
Shimada teaches of an apparatus (Fig 1-2), wherein a first portion of a plurality of surface-mount capacitors (16) have a first nominal capacitance ([0052-0053]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus as taught by Chung in view of Kledzik and Ooyabu, wherein a first portion of the plurality of surface-mount capacitors have a first nominal capacitance as taught by Shimada, in order to provide voltage conversion and stabilization (Shimada, [0002-0022, 0052-0055]).
Regarding Claim 20, Chung in view of Kledzik, Ooyabu and Shimada teaches the limitations of the preceding claim and Shimada further teaches the apparatus (Fig 1-2) of claim 19, wherein a second portion (17) of the plurality of surface-mount capacitors have a second nominal capacitance ([0052-0053]), the second nominal capacitance being greater than ([0052-0053]) the first nominal capacitance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896