DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I and Claims 1-4, 6-12 and 20 in the reply filed on 5/22/2026 is acknowledged.
Claims 5 and 13-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/22/2026.
Claims 9 and 11 are also withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to non-elected species as described below.
Claim 9 recites the limitation wherein “at least a part of the first layer is between a side wall of the first source/drain contact and the second layer”. The first layer is 161 (Fig. 2), first source/drain contact is CA2 (Fig. 2) and the second layer is 162 (Fig. 2), and elected species I (Fig. 2) does not show that 161 is between a sidewall of CA2 and layer 162. This limitation is shown in Fig. 20 / Species IV, where first layer 461 is between a sidewall of CA42 and second layer 462.
Claim 11 recites that the “wherein the first source/drain contact comprises: a first lower surface that is on an upper surface of the first source/drain region and spaced apart from the substrate by a first distance in the vertical direction, and a second lower surface that is on an upper surface of the first layer and spaced apart from the substrate by a second distance in the vertical direction, and wherein the first distance is greater than the second distance.” The limitation wherein “the first distance is greater than the second distance” is only shown in Fig. 19 / Species III.
Information Disclosure Statement
Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered.
Claim Objections
Claim 20 is objected to because of the following informalities:
In line 33, the claim recites, “a second source/drain contact -- disposed that is on and electrically connected -- ”.
Examiner believes that the limitation should recited, “a second source/drain contact -- that is on and electrically connected -- ”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation wherein “a second source/drain region that is between the active cut and is on the second gate electrode on the second active pattern”. It is unclear what the applicant means by the above limitation as the second source/drain region (SD2, Fig. 2) is not on the second gate electrode (G2, Fig. 2). Hence, the claim is indefinite and rejected. For examination purposes, the limitation will be treated as “a second source/drain region that is between the active cut and -- the second gate electrode and is on -- the second active pattern”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (US 2022/0310594 A1).
Re Claim 1, Jeong teaches a semiconductor device (Fig. 3) comprising:
a substrate (101, Fig. 3, para [0020]);
first and second active patterns (active regions 105, marked “105-1” and “105-2” in annotated Fig. 3 below, para [0020]) that are on the substrate (101) and extend in a first horizontal direction (x-axis, Fig. 3), wherein the second active pattern (“105-2”) is spaced apart (see Fig. 3) from the first active pattern (“105-1”) in the first horizontal direction (x-axis);
a first gate electrode (165 of TR1, Fig. 3, paras [0020] – [0021]) that is on the first active pattern (“105-1”) and extends in a second horizontal direction (y-axis, Fig. 3) that is different from the first horizontal direction (x-axis);
a second gate electrode (165 of TR2, Fig. 3, paras [0020] – [0021]) that is on the second active pattern (“105-2”) and extends in the second horizontal direction (y-axis, Fig. 3), wherein the second gate electrode (165 of TR2) is spaced apart (see Fig. 3) from the first gate electrode (165 of TR1) in the first horizontal direction (x-axis);
an active cut trench (marked “trench” in annotated Fig. 3 below) that extends in the second horizontal direction (y-axis, see Fig. 1) and is between (see Fig. 3) the first gate electrode (165 of TR1) and the second gate electrode (165 of TR2), wherein the active cut trench (“trench”) separates the first and second active patterns (“105-1” and “105-2”, see Fig. 3);
an active cut (200b+184, Fig. 3, paras [0057] and [0020]) comprising a first layer (200b) and a second layer (184) on the first layer (200b), wherein the first layer (200b) is on a side wall and a bottom surface of the active cut trench (“trench”, see Fig. 3);
a first source/drain region (marked “150-1” in annotated Fig. 3 below, para [0020]) that is between the first gate electrode (165 of TR1) and the active cut (200b+184) and is on the first active pattern (“105-1”); and
a first source/drain contact (marked “180-1” in annotated Fig. 3 below, para [0020]) that is on and electrically connected to the first source/drain region (“150-1”, see Fig. 3), wherein at least a part of the first source/drain contact overlaps the first layer in a vertical direction (a top part of “180-1” overlaps vertically with the first layer 200b, see Fig. 3).
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Re Claim 2, Jeong teaches the semiconductor device of claim 1, wherein the first source/drain region (“150-1”) contacts the first layer (200b, see Fig. 3).
Re Claim 3, Jeong teaches the semiconductor device of claim 1, wherein at least a part of a lower surface of the first source/drain contact (“180-1”) contacts the first layer (Examiner notes that any surface below the topmost surface of “180-1” can be considered a lower surface, and hence a lower side surface of “180-1” contacts the first layer 200b, see Fig. 3. The claim language does not preclude this treatment).
Re Claim 6, Jeong teaches The semiconductor device of claim 1, further comprising:
a second source/drain region (marked “150-2” in annotated Fig. 3 above, para [0020]) that is between (see Fig. 3) the active cut (200b+184) and the second gate electrode (165 of TR2) and is on the second active pattern (“105-2”); and
a second source/drain contact (marked “180-2” in annotated Fig. 3 above, para [0020]) that is on and is electrically connected to the second source/drain region (“150-2”) between the active cut (200b+184) and the second gate electrode (165 of TR2), wherein at least a part of the second source/drain contact overlaps the first layer in the vertical direction (a top part of “180-2” overlaps vertically with the first layer 200b, see Fig. 3).
Re Claim 7, Jeong teaches the semiconductor device of claim 1, wherein the first layer (200b) and the second layer (184) comprise different materials from each other (200b can be made of SiN, para [0039] while 184 can be made of a silicon oxide, para [0043]).
Re Claim 8, Jeong teaches the semiconductor device of claim 1, wherein a side wall of the first source/drain contact (“180-1”) contacts the second layer (184, see Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2022/0310594 A1), and further in view of Baek et al. (US 2021/0074697 A1).
Re Claim 10, Jeong teaches the semiconductor device of claim 1, wherein the first source/drain contact (“180-1”, Fig. 3) comprises:
a contact filling layer (para [0051], Fig. 3).
Jeong does not disclose that the source/drain contact comprises:
a contact barrier layer that defines a side wall and a bottom surface of the first source/drain contact.
In a related semiconductor art, Baek teaches that the source/drain contact (170, Fig. 6A, para [0071]) can be made of a contact barrier film (170a, Fig. 6A, para [0071]) that defines a side wall and a bottom surface of the first source/drain contact (see Fig. 6A), and contact fill layer (170b, Fig. 6A, para [0071]) on the contact barrier layer (170a).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to include a contact barrier layer into the source/drain contact of Jeong as disclosed by Baek, because it is well-known in the art that the barrier layer prevents material interdiffusion and minimizes contact resistance, thus improving the electrical connection to the source/drain regions of the transistor.
Re Claim 12, Jeong teaches the semiconductor device of claim 1, further comprising:
a first plurality of nanosheets (140 within TR1, Fig. 3, para [0023], also see Examiner comments below) that are on the first active pattern (“105-1”) and spaced apart from each other in the vertical direction (see Fig. 3), wherein the first gate electrode (165 of TR1) at least partially surrounds the first plurality of nanosheets (see Fig. 3); and
a second plurality of nanosheets (140 within TR2, Fig. 3, para [0023], also see Examiner comments below) that are on the second active pattern (“105-2”) and are spaced apart from each other in the vertical direction (see Fig. 3), wherein the second gate electrode (165 of TR2) at least partially surrounds the second plurality of nanosheets (see Fig. 3).
Examiner notes that Jeong does not explicitly state that the channel layers 140 are nanosheets, but does mention that these are gate-all-around type transistors (para [0023]). Related art, Beak discloses that the channel layers of the gate-all-around type transistors can be nanosheets (112NS, Fig. 2, para [0036]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the channel layers of Jeong can be nanosheets as disclosed by Baek, as it is well-known in the art that the nanosheets reduce the areal footprint of the semiconductor device, compacting more transistors within a given volume, thus increasing the efficiency and computing power of the device.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2022/0310594 A1), and further in view of Baek et al. (US 2021/0074697 A1) and Lin et al. (US 2025/0063764 A1).
Re Claim 20, Jeong teaches a semiconductor device (Fig. 3) comprising:
a substrate (101, Fig. 3, para [0020]);
first and second active patterns (active regions 105, marked “105-1” and “105-2” in annotated Fig. 3 above, para [0020]) that are on the substrate (101) and extend in a first horizontal direction (x-axis, Fig. 3), wherein the second active pattern (“105-2”) is spaced apart (see Fig. 3) from the first active pattern (“105-1”) in the first horizontal direction (x-axis);
a first plurality of nanosheets (140 within TR1, Fig. 3, para [0023], also see Examiner comments below) that are on the first active pattern (“105-1”) and spaced apart from each other in the vertical direction (see Fig. 3);
a second plurality of nanosheets (140 within TR2, Fig. 3, para [0023], also see Examiner comments below) that are on the second active pattern (“105-2”) and spaced apart from each other in the vertical direction (see Fig. 3);
a first gate electrode (165 of TR1, Fig. 3, paras [0020] – [0021]) that is on the first active pattern (“105-1”) and extends in a second horizontal direction (y-axis, Fig. 3) that is different from the first horizontal direction (x-axis), wherein the first gate electrode at least partially surrounds the first plurality of nanosheets (see Fig. 3);
a second gate electrode (165 of TR2, Fig. 3, paras [0020] – [0021]) that is on the second active pattern (“105-2”) and extends in the second horizontal direction (y-axis, Fig. 3), wherein the second gate electrode (165 of TR2) is spaced apart (see Fig. 3) from the first gate electrode (165 of TR1) in the first horizontal direction (x-axis), and wherein the second gate electrode at least partially surrounds the second plurality of nanosheets (see Fig. 3);
an active cut trench (marked “trench” in annotated Fig. 3 above) that extends in the second horizontal direction (y-axis, see Fig. 1) and is between (see Fig. 3) the first gate electrode (165 of TR1) and the second gate electrode (165 of TR2), wherein the active cut trench (“trench”) separates the first and second active patterns (“105-1” and “105-2”, see Fig. 3);
an active cut (200b+184, Fig. 3, paras [0057] and [0020]) comprising a first layer (200b) that is on a side wall and a bottom surface of the active cut trench (“trench”, see Fig. 3), wherein the active cut comprises a second layer (184) that is on the first layer (200b), wherein the first layer (200b) contacts side walls of each of the first and second active patterns (side walls of “105-1” and “105-2”, see Fig. 3), and wherein the first layer and the second layer comprise different materials from each other (200b can be made of SiN, para [0039] while 184 can be made of an silicon oxide, para [0043]);
a first source/drain region (marked “150-1” in annotated Fig. 3 above, para [0020]) that is between the first gate electrode (165 of TR1) and the active cut (200b+184) and is on the first active pattern (“105-1”), wherein the first source/drain region (“150-1”) contacts the first layer (200b, see Fig. 3);
a second source/drain region (marked “150-2” in annotated Fig. 3 above, para [0020]) that is between the active cut (200b+184) and the second gate electrode (165 of TR2) and is on the second active pattern (“105-2”), wherein the second source/drain region (“150-2”) contacts the first layer (200b, see Fig. 3);
a first source/drain contact (marked “180-1” in annotated Fig. 3 above, para [0020]) that is on and electrically connected to the first source/drain region (“150-1”, see Fig. 3), wherein a side wall of the first source/drain contact (side wall “180-1”) contacts the second layer (184, see Fig. 3); and
a second source/drain contact (marked “180-2” in annotated Fig. 3 above, para [0020]) that is on and electrically connected to the second source/drain region (“150-2”), and wherein a side wall of the second source/drain contact (side wall “180-2”) contacts the second layer (184, See Fig. 3).
Regarding “nanosheets”, Examiner notes that Jeong does not explicitly state that the channel layers 140 are nanosheets, but does mention that these are gate-all-around type transistors (para [0023]). Related art, Beak discloses that the channel layers of the gate-all-around type transistors can be nanosheets (112NS, Fig. 2, para [0036]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the channel layers of Jeong can be nanosheets as disclosed by Baek, as it is well-known in the art that the nanosheets reduce the areal footprint of the semiconductor device, compacting more transistors within a given volume, thus increasing the efficiency and computing power of the device.
Jeong discloses that the lower side walls of the first source/drain-contact (“180-1”) and the second source/drain-contact (“180-2”) contact the second layer (184), but fails to disclose an additional lower surface of the first source/drain-contact and the second source/drain-contact contacting the first layer (200b, Fig. 3).
In a related semiconductor art, Lin teaches that the source/drain contact structure (294/296, Fig. 5A, para [0132]) adjacent to the isolation structure (252) can extend toward the isolation structure (252) to have a greater width such that a lowermost surface of the contact structure (294/296) contacts the isolation structure (252, see Fig. 5A). The greater width decreases the contact resistance between the contact structure and the source/drain region (para [0132]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to increase the width of the S/D contact structure (180, Fig. 3, Jeong) adjacent to the isolation structure (200b+184, Fig. 3) of the device of Jeong as disclosed by Lin (Fig. 5A, Lin), such that a lowermost surface of the first/second contact structure (lowermost surface of “180-1” / “180-2”, Fig. 3 of Jeong, similar to lowermost surface of 294/296, Fig. 5A of Lin) contacts the first layer of the isolation structure (first layer 200b, Fig. 3 of Jeong, similar to isolation structure 252, Fig. 5A of Lin). The greater width of the S/D contact decreases the contact resistance between the contact structure and the source/drain region (para [0132], Lin).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 is allowable for at least the reasons of, “a silicide layer that is between the first source/drain region and the first source/drain contact, wherein at least a part of the silicide layer contacts the first layer.” Prior art Jeong, as applied to independent claim 1 above fails to teach a silicide layer. Related art, Lin et al. (US 2025/0063764 A1) teaches a silicide layer (284, Fig. 3A, para [0128]) between the source contact (294, Fig. 3A, para [0130]) and S/D regions (194, Fig. 3A, para [0078]) but fails to teach that the silicide layer contacts the isolation structure. This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion, when taken in context of the whole claim and in view of the independent claim 1, as a whole.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ko et al. (US 2021/0343597 A1) also teaches a similar device as the applicant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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