Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on August 3, 2026 is acknowledged. Examiner considers applicant’s arguments persuasive that species are coextensive and overlap. Therefore, the restriction requirement as set forth in the office action mailed on June 1, 2026, is hereby withdrawn.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6-9, 15-16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US Patent No. 10,510,724), hereinafter referred to as Yoo, in view of He et al. (Pub. No. US 20230197543 A1), hereinafter referred to as He.
Regarding claim 1, Yoo teaches a semiconductor package comprising: a substrate (Fig. 1, buffer layer 110; Col. 2, line 34 - Col. 3, line 57); a first chip structure and a second chip structure on the substrate, the first chip structure adjacent to the second chip structure, the first chip structure including a first step portion on an upper portion of the first chip structure, and the second chip structure including a second step portion on an upper portion of the second chip structure (Fig. 5D &5E, buffer layer 110, semiconductor chip stack 530, provisional trench 163, upper semiconductor chip 157; Col. 11 lines 22-60); and a mold sealing the first chip structure and the second chip structures (Fig. 5F, chip sealing material 180; Col. 11, lines 61-67). However, Yoo does not explicitly teach the mold including first fillers distributed in a first region between the first step portion and the second step portion, and second fillers distributed in a second region below the first region, and a first content of the first fillers in the mold is greater than a second content of the second fillers in the mold.
He teaches the mold including first fillers distributed in a first region, and second fillers distributed in a second region below the first region, and a first content of the first fillers in the mold is greater than a second content of the second fillers in the mold (Figs. 1A-1B, first material layer 112, first filler 113, second material layer 116, second fillers 117; ¶26, 30-32).
Yoo and He are analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the mold of Yoo with the teachings of He such that the mold includes first fillers distributed in a first region between the first step portion and the second step portion, and second fillers distributed in a second region below the first region, and a first content of the first fillers in the mold is greater than a second content of the second fillers in the mold. For the purpose of improving the mechanical and thermal properties
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of the device, as recognized by He.
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Regarding claim 2, Yoo further teaches a first width of the first region is greater than a second width of the second region (Figs. 5E and 5F, width W7; Col. 11 lines 43-67).
Regarding claim 6, Yoo does not teach the first fillers and the second fillers include a same material.
He teaches the first fillers and the second fillers include a same material (Fig. 1B, first fillers 113, second fillers 117; ¶30,32).
Yoo and He are analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the mold of Yoo with the teachings of He such that the first fillers and the second fillers include a same material. For the purpose of improving the mechanical and thermal properties of the device, as recognized by He.
Regarding claim 7, Yoo does not teach an average diameter of the first fillers is about 10 µm or more, and an average diameter of the second fillers is less than about 10 µm.
He teaches an average diameter of the first fillers is about 10 µm or more, and an average diameter of the second fillers is less than about 10 µm (Fig. 1B, first fillers 113, second fillers 117; ¶30,32).
Yoo and He are analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the mold of Yoo with the teachings of He such that an average diameter of the first fillers is about 10pm or more, and an average diameter of the second fillers is less than about 10pm. For the purpose of improving the mechanical and thermal properties of the device, as recognized by He.
Regarding claim 8, Yoo further teaches the first step portion of the first chip structure defines a first recess extending along at least a portion of a circumference of the first chip structure in a plane, and the second step portion of the second chip structure defines a second recess extending along at least a portion of a circumference of the second chip structure in a plane (Figs. 2 & 4A, upper semiconductor chip 157, trench 160; Col. 8, lines 14-40 and Col. 10, lines 4-23).
Regarding claim 9, Yoo further teaches the first step portion and the second step portion respectively have a first side and a second side opposing each other, the first recess is on the first side of the first step portion, and the second recess is on the second side of the second step portion (Fig. 5E, provisional trench 163; Col. 11, lines 43-60).
Regarding claim 15, Yoo further teaches the substrate includes an interconnection circuit electrically connected to at least one of the first chip structure and the second chip structure, the semiconductor package further comprising a plurality of connection bumps below the substrate and electrically connected to the interconnection circuit (Figs. 5A-5D, buffer layer 110, semiconductor chip stack 530; Col. 3, lines 58-65 and Col. 10, line 52- Col. 11, line 42).
Regarding claim 16, Yoo teaches a semiconductor package comprising: a substrate (Fig. 1, buffer layer 110; Col. 2, line 34 - Col. 3, line 57); a plurality of chip structures including a first chip structure and a second chip structure on the substrate, the first chip structure adjacent to the second chip structure (Fig. 5D, semiconductor chip stack 530; Col. 11, lines 22-42); and a mold covering upper and side surfaces of each of the plurality of chip structures, wherein the first chip structure includes a first step portion defining a first recess in an upper portion of the first chip structure (Fig. 5D-5F, chip sealing material 180, semiconductor chip stack 530, provisional trench 163, upper semiconductor chip 157; Col. 11 lines 22-67). However, Yoo does not explicitly teach the mold including first fillers in a first region between the first step portion of the first chip structure and the second chip structure, and second fillers in a second region below the first region, the second region is between a side surface of the first chip structure and a side surface of the second chip structure, and a second content of the second fillers in the second region is less than a first content of the first fillers in the first region.
He teaches the mold including first fillers in a first region, and second fillers in a second region below the first region, the second region is between a side surface of the first chip structure and a side surface of the second chip structure, and a second content of the second fillers in the second region is less than a first content of the first fillers in the first region (Figs. 1A-1B, first material layer 112, first filler 113, second material layer 116, second fillers 117; ¶26, 30-32).
Yoo and He are analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the mold of Yoo with the teachings of He such that the mold includes first fillers in a first region between the first step portion of the first chip structure and the second chip structure, and second fillers in a second region below the first region, the second region is between a side surface of the first chip structure and a side surface of the second chip structure, and a second content of the second fillers in the second region is less than a first content of the first fillers in the first region. For the purpose of improving the mechanical and thermal properties of the device, as recognized by He.
Regarding claim 18, Yoo further teaches the second chip structure includes a second step portion defining a second recess in an upper portion of the second chip structure, and the first region is between the first step portion and the second step portion (Fig. 5E, semiconductor chip stack 530, provisional trench 163, upper semiconductor chip 157; Col. 11 lines 22-60).
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of He as applied to claim 2 above, and further in view of Lu et al. (US Patent No. 9,620,430), hereinafter referred to as Lu.
Regarding claim 3, Yoo teaches a maximum width of the trench may be in a range in the from about 10 µm to about 2000 µm (Figs. 5E and 5F, width W7; Col. 11 lines 43-67). However, Yoo in view of He does not explicitly teach the first width is at least twice the second width.
Lu teaches spacing between neighboring dies being between about 5 µm and 500 µm (Fig. 4C, width W of trenches 54, neighboring dies 44, spacing S; Col. 3, lines 35-61)
Yoo, He, and Lu are all analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Yoo in view of He with the teachings of Lu such that the first width is at least twice the second width. For the purpose of balancing the reliability of the device and optimization of the electrical, thermal, and mechanical characteristics of the device with the desire for smaller devices.
Regarding claim 4, Yoo in view of He does not explicitly teach the second width ranges from about 0.2 mm to about 0.6 mm. Lu teaches spacing between neighboring dies being between about 5 µm and 500 µm (Fig. 4C, width W of trenches 54, neighboring dies 44, spacing S; Col. 3, lines 35-61)
Yoo, He, and Lu are all analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Yoo in view of He with the teachings of Lu such that the second width ranges from about 0.2 mm to about 0.6 mm. For the purpose of balancing the reliability of the device and optimization of the electrical, thermal, and mechanical characteristics of the device with the desire for smaller devices.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of He as applied to claim 1 above, and further in view of Karhade et al. (US Patent No. 12,243,793), hereinafter referred to as Karhade.
Regarding claim 5, Yoo in view of He teaches a first content of the first fillers in the mold is greater than a second content of the second fillers in the mold (See Claim 1). However, Yoo in view of He does not explicitly teach the first content ranges from about 60 wt% to about 70 wt%, and the second content ranges from about 50 wt% to about 60 wt%.
Karhade et al. teaches the first content ranges from about 60 wt% to about 70 wt% (Fig. 22, dielectric material 197; Col. 9, line 42 – Col. 10, line 20), and the second content ranges from about 50 wt% to about 60 wt% (Fig. 22, dielectric material 199; Col. 9, line 42 – Col. 10, line 20).
Yoo, He, and Karhade are all analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Yoo in view of He with the teachings of Lu such that the first content ranges from about 60 wt% to about 70 wt%, and the second content ranges from about 50 wt% to about 60 wt%. For the purpose of optimizing the mechanical properties of the mold fillers by adjusting the weight content based on the location of the fillers within the device, as recognized by both He and Karhade.
Claim(s) 10-11, 14, 17, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of He as applied to claims 1 and 16 above, and further in view of Seol et al. (Pub. No. US 20210082881 A1), hereinafter referred to as Seol.
Regarding claim 10, Yoo further teaches the first chip structure includes a first chip body and the first step portion (Fig. 5E, semiconductor chip stack 530, provisional trench 163, upper semiconductor chip 150, upper portion of the upper semiconductor chip 157, lower portion of the upper semiconductor chip 158; Col. 11, lines 22-67), and the second chip structure includes a second chip body and the second step portion (Fig. 5E, semiconductor chip stack 530, provisional trench 163, upper semiconductor chip 150, upper portion of the upper semiconductor chip 157, lower portion of the upper semiconductor chip 158; Col. 11, lines 22-67). However, Yoo in view of He does not explicitly teach a first spacer on the first chip body, and a first adhesive film layer between the first chip body and the first spacer, the first spacer including the first step portion and a second spacer on the second chip body, and a second adhesive film layer between the second chip body and the second spacer, the second spacer including the second step portion.
Seol teaches a first spacer on the first chip body, and a first adhesive film layer between the first chip body and the first spacer (Fig. 3, upper chips 21, adhesive layer 53, thermally conductive spacer 55; ¶24).
Yoo, He, and Seol are all analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Yoo in view of He with the spacer of Seol such that there is a first spacer on the first chip body, and a first adhesive film layer between the first chip body and the first spacer, the first spacer including the first step portion, and the second chip structure includes a second spacer on the second chip body, and a second adhesive film layer between the second chip body and the second spacer, the second spacer including the second step portion. For the purpose of improving the thermal characteristics of the device, as recognized by Seol.
Regarding claim 11, Yoo in view of He does not explicitly teach a bonding wire electrically connecting at least one of the first chip body and the second chip body to the substrate.
Seol teaches a bonding wire electrically connecting at least one of the first chip body and the second chip body to the substrate (upper chips 21, wires 25, substrate 10; ¶13).
Yoo, He, and Seol are all analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Yoo in view of He with the teachings of Seol such that a bonding wire electrically connects at least one of the first chip body and the second chip body to the substrate. For the purpose of the benefits of using bond wires such as reduced manufacturing costs.
Regarding claim 14, Yoo teaches the first chip body includes one or more first semiconductor chips, and the second chip body includes one or more second semiconductor chips (Fig. 5D, first, second, and third intermediate semiconductor chips 131, 132, 133, upper semiconductor chip 150, semiconductor chip stack 530; Col. 11, lines 22-42).
Regarding claim 17, Yoo further teaches the first chip structure includes a plurality of first semiconductor chips stacked in a vertical direction, a base portion on the plurality of first semiconductor chips, and the first step portion is on the base portion, wherein the plurality of first semiconductor chips are electrically connected to the substrate (Fig. 5E, buffer layer 110, first, second, and third intermediate semiconductor chips 131, 132, 133, upper semiconductor chip 150, semiconductor chip stack 530, provisional trench 163, upper portion of the upper semiconductor chip 157, lower portion of the upper semiconductor chip 158; Col. 3, lines 58-65 and Col. 10, line 52 - Col. 11, line 67). However, Yoo in view of He does not explicitly teach a first spacer, the first spacer including a base portion on the plurality of first semiconductor chips, and the first step portion is on the base portion, and the first spacer is electrically insulated from the substrate.
Seol teaches teach a first spacer, the first spacer including a base portion on the plurality of first semiconductor chips, and the first spacer is electrically insulated from the substrate (Fig. upper chips 21, insulating layer 40, chimney 50, thermally conductive spacer 55; ¶15-18).
Yoo, He, and Seol are all analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Yoo in view of He with the spacer of Seol such that the first chip structure includes a plurality of first semiconductor chips stacked in a vertical direction, and a first spacer, the first spacer including a base portion on the plurality of first semiconductor chips, and the first step portion is on the base portion, wherein the plurality of first semiconductor chips are electrically connected to the substrate, and the first spacer is electrically insulated from the substrate. For the purpose of improving the thermal characteristics of the device, as recognized by Seol.
Regarding claim 19, Yoo teaches a semiconductor package comprising: a substrate (Fig. 1, buffer layer 110; Col. 2, line 34 - Col. 3, line 57); a first chip structure and a second chip structure on the substrate, the first chip structure adjacent to the second chip structure (Fig. 5D, buffer layer 110, semiconductor chip stack 530; Col. 11, lines 22-67); and a mold sealing the first chip structure and second chip structures (Fig. 5F, chip sealing material 180; Col. 11, lines 61-67); wherein the first chip structure includes a first chip body, the first chip body including a plurality of first semiconductor chips, a first base portion and a first step portion on the first base portion, and the first base portion is on the first chip body (Figs. 5D-5E, first, second, and third intermediate semiconductor chips 131, 132, 133, upper semiconductor chip 150, semiconductor chip stack 530, provisional trench 163, upper portion of the upper semiconductor chip 157, lower portion of the upper semiconductor chip 158; Col. 11, lines 22-67), and the second chip structure includes a second chip body, the second chip body including at least one dummy chip or a plurality of second semiconductor chips, and the second base portion is on the second chip body (Figs. 5D-5E, first, second, and third intermediate semiconductor chips 131, 132, 133, upper semiconductor chip 150, semiconductor chip stack 530, provisional trench 163, upper portion of the upper semiconductor chip 157, lower portion of the upper semiconductor chip 158; Col. 11, lines 22-67), wherein a distance between the first step portion and the second step portion is greater than a distance between the first chip body and the second chip body (Figs. 5E, width W7; Col. 11 lines 43-67). However, Yoo in view of He does not explicitly teach the first chip structure including a first spacer, the first spacer including a first base portion and a first step portion on the first base portion, and a second spacer, the second spacer including a second base portion and a second step portion on the second base portion.
Seol teaches the chip structure including a spacer (Fig. 3, upper chips 21, adhesive layer 53, thermally conductive spacer 55; ¶24).
Yoo, He, and Seol are all analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Yoo in view of He with the spacer of Seol such that the first chip structure includes a first spacer, the first spacer including a first base portion and a first step portion on the first base portion, and a second spacer, the second spacer including a second base portion and a second step portion on the second base portion. For the purpose of improving the thermal characteristics of the device, as recognized by Seol.
Regarding claim 20, Yoo further teaches the first chip structure and the second chip structure are adjacent to each other along a first direction, wherein in the first direction, a width of the first step portion is less than a width of the first base portion, and a width of the second step portion is less than a width of the second base portion (Fig. 5E, semiconductor chip stack 530, width W3, width W7; Col. 11 lines 22-67).
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of He and Seol as applied to claim 10 above, and further in view of Kim (Pub. No. US 20210167054 A1).
Regarding claim 12, Yoo further teaches the first chip body includes one or more first semiconductor chips (Fig. 5D, first, second, and third intermediate semiconductor chips 131, 132, 133, upper semiconductor chip 150, semiconductor chip stack 530; Col. 11, lines 22-42). However, Yoo in view of He and Seol does not explicitly teach the second chip body includes at least one dummy chip.
Kim teaches the second chip body includes at least one dummy chip (Fig. 2, first semiconductor chip 300, dummy chip 400; ¶22-35).
Yoo, He, Seol, and Kim are all analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Yoo in view of He and Seol with the teachings of Kim such that the first chip body includes one or more first semiconductor chips, and the second chip body includes at least one dummy chip. For the purpose of compensating of a height difference between chip stacks to increase the planarity of the device to aid in subsequent processing steps, as recognized by Kim.
Regarding claim 13, Yoo further teaches a third chip structure adjacent to the second chip structure, the third chip structure including a third chip body, and a third step portion (Figs. 5D-5E, first, second, and third intermediate semiconductor chips 131, 132, 133, upper semiconductor chip 150, semiconductor chip stack 530, provisional trench 163, upper portion of the upper semiconductor chip 157, lower portion of the upper semiconductor chip 158; Col. 11, lines 22-67). However, Yoo does not explicitly teach a third spacer on the third chip body, and a third adhesive film layer between the third chip body and the third spacer, the third spacer including a third step portion, wherein the mold includes third fillers distributed in a third region between the second step portion and the third step portion, and fourth fillers distributed in a fourth region below the third region, and a third content of the third fillers is greater than a fourth content of the fourth fillers.
He teaches the mold includes third fillers distributed in a third region between, and fourth fillers distributed in a fourth region below the third region, and a third content of the third fillers is greater than a fourth content of the fourth fillers (Figs. 1A-1B, first material layer 112, first filler 113, second material layer 116, second fillers 117; ¶26, 30-32).
Yoo and He are analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the mold of Yoo with the teachings of He such that the mold includes third fillers distributed in a third region between the second step portion and the third step portion, and fourth fillers distributed in a fourth region below the third region, and a third content of the third fillers is greater than a fourth content of the fourth fillers. For the purpose of improving the mechanical and thermal properties of the device, as recognized by He.
However, Yoo in view of He still does not explicitly teach a third spacer on the third chip body, and a third adhesive film layer between the third chip body and the third spacer, the third spacer including a third step portion.
Seol teaches a third spacer on the third chip body, and a third adhesive film layer between the third chip body and the third spacer (Fig. 3, upper chips 21, adhesive layer 53, thermally conductive spacer 55; ¶24).
Yoo, He, and Seol are all analogous art as they are in the same field of endeavor of semiconductor devices and packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Yoo in view of He with the spacer of Seol such that there is a third spacer on the third chip body, and a third adhesive film layer between the third chip body and the third spacer, the third spacer including a third step portion. For the purpose of improving the thermal characteristics of the device, as recognized by Seol.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN ALEXANDER TUTTLE whose telephone number is (571)272-7055. The examiner can normally be reached Monday - Friday, 9 am - 5 pm ET.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./Examiner, Art Unit 2897
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