DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claims 3 and 6 are objected to because of the following informalities: the first instance of “a GPU encoding engine” occurs in claim 1, correct the instance of “a GPU encoding engine” in claims 3 and 6 to ‘the GPU encoding engine’. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 14-20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As to claim 14, the limitation a “first Peripheral Component Interconnect Express (PCle) device comprising… a central processing unit (CPU)” is supported by the Specification paragraph [0039] which indicates “the DPU 204 is a new class of programmable processor that combines three key elements, including, for example: 1) an industry-standard, high-performance, software-programmable CPU (single-core or multi-core CPU), tightly coupled to the other SoC components”; however, there is not support for any actions of the first PCIe device, including the claimed synchronization actions, being under taken “without involvement by the CPU” of the first PCIe device. The Specification only supports the claim of “without involvement by the CPU” with respect to the claimed “host device” and embodiment in which the separate “host device” is indicated as a CPU separate of the first PCIe. Claims 15-18 and 20 are rejected due to dependence on claim 14.
As to claim 19, the claim includes the same discrepancies as claim 14 regarding the CPU limitations.
Claims 1-6, 8-11, and 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the semaphore memory" in 14. There is insufficient antecedent basis for this limitation in the claim because the first instance of “a semaphore memory” was removed by the amendments. Claims 2-6 are rejected due to the same discrepancy or due to dependence on the rejected claim.
Claim 8 recites the limitation "the semaphore memory" in 12. There is insufficient antecedent basis for this limitation in the claim because the first instance of “a semaphore memory” was removed by the amendments. Claims 9-11 are rejected due to the same discrepancy or due to dependence on the rejected claim.
Claim 14 recites the limitation "the semaphore memory" in 15. There is insufficient antecedent basis for this limitation in the claim because the first instance of “a semaphore memory” was removed by the amendments. Claims 15-18 and 20 are rejected due to the same discrepancy or due to dependence on the rejected claim.
Claim 19 recites the limitation "the semaphore memory" in 14. There is insufficient antecedent basis for this limitation in the claim because there is no first instance ‘a semaphore memory’.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Amento et al. (US Pub. No. 2020/0151127), hereinafter referred to as Amento, in view of Shirizly et al. (US Pub. No. 2024/0028550), hereinafter referred to as Shirizly, further in view of Raduchel et al. (US Pub. No. 2018/006355), hereinafter referred to as Raduchel.
Referring to claim 1, Amento discloses a computing system comprising: a central processing unit (CPU) (fig. 1, CPU 110) to execute over a network (fig. 1, network links 190; [0016-0017]); a graphics processing unit (GPU) (fig. 1, GPU 130) to render a video bitstream (a video stream, [0031]) and store the video bitstream in a GPU-mapped system memory buffer (a memory buffer of the GPU may be created at launch time to receive streaming network packets, [0013]); and a data processing unit (DPU) (fig. 1, NIC 120) coupled to the CPU and the GPU, the DPU comprising memory (fig. 1, 122) and a hardware synchronization mechanism to synchronize direct memory access (DMA) transfers of the bitstream from the GPU-mapped system memory buffer to the memory of the DPU (command to the DMA engine of NIC 120 to read from the pinned memory pool of shared memory 132 at GPU…NIC 120 may read out a portion of the pinned memory pool based upon a size of the transfer… copied into NIC memory…in one example, the packet(s) may be loaded into one or more transmit, [0033-0034]), wherein the hardware synchronization mechanism is configured to: (i) poll the semaphore memory to determine when a semaphore value, written by the GPU (GPU setting a polling flag, [0046]), indicates the video bitstream is available for transfer (a polling flag…when read, indicates whether or not the packet processing is complete, [0046]), and (ii) initiate the DMA transfer in response to the semaphore value (read the polling flag, determine the GPU-based packet processing is completed, and notify the NIC that the processing of at least the first packet is completed (and/or instruct the NIC to read at least the first packet from the memory buffer), [0046]; data that is read via the DMA transfer, [0046]), wherein the DPU is to send streaming data over the network, the streaming data comprising the video bitstream (streaming data processing applications, [0014]; NIC 120 may also advance a read pointer…data that is read via the DMA transfer… the packet(s) are transmitted via transceivers 124 and network links, [0033-0034]).
While Amento discloses NIC transfer operations “without involvement by the CPU” (NIC 120 may proceed with the DMA transfer without instruction from the CPU 110, [0028]), and polling of a flag (i.e., “a semaphore”) indicating available data, the polling mechanism described in paragraph [0046] appears to indicate involvement of the CPU instead of being “in the DPU” and “without involvement by the CPU.” Additionally, Amento does not appear to explicitly disclose “a game application to be streamed to a client device”, “render frames of the game application and encode a video bitstream of the rendered frames”, and “a GPU encoding engine”.
However, in a similar endeavor of managing network transmissions, Shirizly disclose the polling performed by the NIC (the hardware (e.g., NIC or NIC PE) may perform polling of the hardware interface to see if any new work is available, [0033]), which teaches a polling embodiment being “in the DPU” and “without involvement by the CPU.”
Furthermore, Raduchel discloses “a game application to be streamed to a client device” (a game that is being remotely accessed on the client device 120 and running locally on a virtual machine on the server system, [0047]), “render frames of the game application and encode a video bitstream of the rendered frames” (the GPU of the NEGPM 116B can render video frames in a framebuffer, encode video frames, [0060]), and a GPU encoding engine (GPU chip 310 further includes a rendering module 312 and an encoding module 314, [0078]),
Amento and Raduchel are analogous art because they are from the same field of endeavor, graphics processing systems.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Amento, Shirizly, and Raduchel before him or her, to modify the network system of Amento to include the NIC polling technique of Shirizly because the technique would reduce CPU operational responsibilities which reduces CPU load. Additionally it would have been obvious to modify the graphics processing system of Amento to perform game application processing as taught by Raduchel in order to facilitate access to remote resources for improved application processing.
The suggestion/motivation for doing so would have been to offload packet handling to the NIC (Shirizly: [0078]) and improve performance in video game data streaming across a network (Raduchel: [0066]).
Therefore, it would have been obvious to combine Amento, Shirizly, and Raduchel to obtain the invention as specified in the instant claim.
As to claim 2, the combination of Amento, Shirizly, and Raduchel discloses the DPU further comprises hardware engines and one or more processing cores to perform network operations (Amento: GPU 130 may include a host interface 135, e.g., a PCI or PCIe transceiver (PHY) for communicating with CPU 110 and NIC 120 via bus 180. In addition, GPU 130 may include a plurality of streaming multiprocessors (SMs) 139, a shared memory 132 that is accessible to the plurality of SMs 139, and a scheduler 131 for distributing kernels and data processing assignments to various SMs…core(s) of the SMs 139, performs various routing operations; [0018]) and encryption on the video bitstream and an audio bitstream and send the streaming data to the client device over the network (Raduchel: use encryption protocols in generating the network packet data 204b to be transmitted to the client device, [0076]; applications such as multiplayer games and audio/video conferencing applications, [0120]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Amento, Shirizly, and Raduchel before him or her, to modify the graphics processing system of Amento to encryption as taught by Raduchel because encryption provides security for data processing and transmission.
The suggestion/motivation for doing so would have been to secure sensitive transmission data (Raduchel: [0141]).
Therefore, it would have been obvious to combine Amento, Shirizly, and Raduchel to obtain the invention as specified in the instant claim.
As to claim 3, the combination of Amento, Shirizly, and Raduchel discloses the GPU comprises a GPU rendering engine and a GPU encoding engine (Raduchel: GPU chip 310 further includes a rendering module 312 and an encoding module 314, [0078]), wherein the GPU rendering engine is to render the frames of the game application, and wherein the GPU encoding engine is to encode the video bitstream into an encoded bitstream, store the encoded bitstream in the GPU-mapped system memory buffer (Amento: shared ring buffer that is readable and writeable by both the NIC 120 and GPU 130, [0022]; Raduchel: a video renderer configured to render the one or more frames of the video data to be transmitted to the client device, (ii) a video encoder configured to encode the one or more rendered frames of the video data, and (iii) graphics memory for temporarily storing the encoded video data, [0020]), and output a completion indication to a semaphore memory (Amento: GPU setting a polling flag…indicates whether or not the packet processing is complete, [0046])).
The suggestion/motivation for doing so would have been to combine remains as indicated above.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Amento, Shirizly, and Raduchel, as applied to claims 1-3 above, further in view of Borkovic et al. (US Patent No. 11847507), hereinafter referred to as Borkovic.
As to claim 4, while the combination of Amento, Shirizly, and Raduchel discloses the DPU is to poll the semaphore memory and a DMA transfer of a portion of the video bitstream, the combination is silent regarding the polling scheme and therefore does not appear to explicitly disclose periodically polling and determine a size for a DMA transfer.
However, one of ordinary skill would recognize that periodic polling as one of a finite number of well-known solutions available polling.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Amento, Shirizly, and Raduchel before him or her, to implement the anticipated polling technique according to a periodic polling solution, because the combination demonstrates there was a need to check the semaphore and one of ordinary skill in the art would recognize periodic polling as one of a finite number of predictable solutions for checking a status, with a reasonable expectation of success. The rationale to support a conclusion that the claim would have been obvious is that "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense (MPEP2143.I.E).
Furthermore, Borkovic teaches determine a size for a DMA transfer (data scheduler 750 may determine the size of each set of consecutive DMA transfers; col. 21, lines 55-60).
Amento, Shirizly, Raduchel, and Borkovic are analogous art because they are from the same field of endeavor, direct memory access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Amento, Shirizly, Raduchel, and Borkovic before him or her, to modify the graphics processing system of the combination of Amento, Shirizly, and Raduchel to include the data scheduler of Borkovic in order to manage DMA transfers.
The suggestion/motivation for doing so would have been to optimize data transfers (Borkovic: col. 21, lines 45-60).
Therefore, it would have been obvious to combine Amento, Shirizly, Raduchel, and Borkovic to obtain the invention as specified in the instant claim.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Amento, Shirizly, and Raduchel, as applied to claims 1-3 above, further in view of George et al. (US Pub. No. 2013/0293558), hereinafter referred to as George.
As to claim 5, while Amento teaches the CPU (fig. 1, 110), the memory of the DPU (fig. 1, memory 112 of NIC 120), and a communication channel between the CPU and GPU (fig. 1, bus 180), and Raduchel teaches the game application and an audio bitstream (applications such as multiplayer games and audio/video conferencing applications, [0120]), the combination does not appear to explicitly disclose the CPU to capture and send the audio bitstream.
However, George teaches the CPU to capture and send the audio bitstream (Audio data is provided to the CPU 302 …audio data may be processed by the CPU…GPU 304 is additionally responsible for processing all video data…audio and video data may be stored, [0047]).
Amento, Shirizly, Raduchel, and George are analogous art because they are from the same field of endeavor, graphics processing systems.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Amento, Shirizly, Raduchel, and George before him or her, to modify the graphics processing system of the combination of Amento, Shirizly, and Raduchel to include the separate audio processing as taught by George as a typical audio/video graphics processing configuration.
The suggestion/motivation for doing so would have been to optimize the utilization of the processing components (George: [0010-0011]).
Therefore, it would have been obvious to combine Amento, Shirizly, Raduchel, and George to obtain the invention as specified in the instant claim.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Amento, Shirizly, and Raduchel, as applied to claims 1-3 above, further in view of Bolz et al. (US Pub. No. 2013/0162661), hereinafter referred to as Bolz.
As to claim 6, Amento discloses the GPU is to provide a mapping of the GPU- mapped system memory buffer to the DPU (GPU 130 may allocate the memory pool for use by a DMA engine of NIC 120, [0022]), and Raduchel discloses a GPU encoding engine of the GPU ((the GPU of the NEGPM 116B can render video frames in a framebuffer, encode video frames, [0060])) and upon completion of encoding a portion of the video bitstream (Once the GPU completes video compression, encoded video data, [0008]).
While the setting the polling flag of Amento teaches “a semaphore in the semaphore memory” accessible by the GPU, and Shirizly teaches accessible by the DPU, the combination is silent regarding steps of clearing flag, and therefore does not appear to explicitly disclose the step to release a semaphore in a semaphore memory.
However, Bolz teaches the step to release a semaphore in a semaphore memory (GPU writes to a synchronization semaphore in memory which indicates the task that was completed…there will be a semaphore release (e.g., with the AID) written to the release synchronization semaphore that was allocated, [0072-0074]).
Amento, Shirizly, Raduchel, and Bolz are analogous art because they are from the same field of endeavor, graphics processing systems.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Amento, Shirizly, Raduchel, and Bolz before him or her, to modify the graphics processing system of the combination of Amento, Shirizly, and Raduchel to include the semaphore release technique of Bolz because the release would provide indication of completion.
The suggestion/motivation for doing so would have been to provide completion tracking (Bolz: [0071]).
Therefore, it would have been obvious to combine Amento, Shirizly, Raduchel, and Bolz to obtain the invention as specified in the instant claim.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Agostini et al. (US Pub. No. 2024/0078185), hereinafter referred to as Agostini, in view of Shirizly.
Referring to claim 8, Agostini discloses a computing system (fig. 1) comprising: a central processing unit (CPU) (fig. 1, CPU(s) 110); a first Peripheral Component Interconnect Express (PCIe) device (fig. 1, GPU(s) 116) coupled to the CPU (fig. 1, GPU(s) coupled to CPU(s); connection 120…a Peripheral Component Interconnect Express (“PCIe”) bus…connect the first GPU(s) 116 to the first CPU(s), [0052]); a second PCIe device (fig. 1, Network Interface 114) coupled to the CPU and the first PCIe device (fig. 1, Network Interface coupled to GPU(s) and CPU(s) by 120; first network interface 114 is connected to the first GPU(s) 116 by a connection 120…a Peripheral Component Interconnect Express (“PCIe”) bus…also connect the first GPU(s) 116 to the first CPU(s), [0052]); and a hardware synchronization mechanism to synchronize streaming data from the first PCIe device to the second PCIe device, wherein the hardware synchronization mechanism is configured to: (i) poll the semaphore memory to determine when a semaphore value, written by the first PCIe device, indicates the streaming data is available for transfer, and (ii) initiate transfer of the streaming data in response to the semaphore value (network interface…may be informed (e.g., by…polling the semaphore 140B, and/or the like) of the availability of the output data 154. Then, the first network interface 114 (e.g., the network interface application 122C) may retrieve the output data 154 (see FIGS. 1, 4, and 7) from the output buffer 452A and transmit the output data; [0089]).
While Agostini discloses NIC transfer operations “without involvement by the CPU” (CPU(s) 110 may not participate…In addition to the receive function, the GPU application 122B may perform a processing function in which the GPU application 122B may process the packet data 144 to produce the output data 154, [0067]) and polling of a semaphore indicating available data, the polling mechanism described in paragraph [0090] appears to indicate involvement of the CPU instead of being “in the second PCIe device” and “without involvement by the CPU.”
However, in a similar endeavor of managing network transmissions, Shirizly disclose the polling performed by the NIC (the hardware (e.g., NIC or NIC PE) may perform polling of the hardware interface to see if any new work is available, [0033]), which teaches a polling embodiment being “in the second PCIe device” and “without involvement by the CPU.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Agostini and Shirizly before him or her, to modify the network system of Agostini to include the NIC polling technique of Shirizly because the technique would reduce CPU operational responsibilities which reduces CPU load.
The suggestion/motivation for doing so would have been to offload packet handling to the NIC (Shirizly: [0078]).
Therefore, it would have been obvious to combine Agostini and Shirizly to obtain the invention as specified in the instant claim.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Agostini in view of Shirizly, as applied to claim 8 above, further in view of Raduchel.
As to claim 9, Agostini discloses the first PCIe device is a graphics processing unit (GPU) (fig. 1, GPU(s) 116), wherein the second PCIe device is a data processing unit (DPU) (fig. 1, Network Interface 114).
The combination of Agostini in view of Shirizly does not appear to explicitly disclose the DPU is a programmable data center infrastructure on a chip, and wherein the data is an encoded bitstream associated with a game executed by the CPU.
However, Raduchel discloses the DPU is a programmable data center infrastructure on a chip (circuit IP blocks, including CPUs, GPUs, NICs…custom low-power system-integrated chips (SoCs)…installed in data centers, [0111]; ), and wherein the data is an encoded bitstream associated with a game executed by the CPU (computer processing unit (CPU) of the server system then further processes the encoded video data using a set of video streaming protocol and then converts the encoded video data to stream data that can be rendered on a client device, [0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Agostini, Shirizly, and Raduchel before him or her, to modify the network system of Agostini to include game application processing as taught by Raduchel in order to facilitate access to remote resources for improved application processing.
The suggestion/motivation for doing so would have been to improve performance in video game data streaming across a network (Raduchel: [0066]).
Therefore, it would have been obvious to combine Agostini, Shirizly, and Raduchel to obtain the invention as specified in the instant claim.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Agostini in view of Shirizly, as applied to claim 8 above, further in view of Amento.
As to claim 10, Agostini discloses the first PCIe device is to store the streaming data in a system memory buffer (shared data structure(s) 134 may include one or more buffers 136…For each data processing application (e.g., the GPU application 122B,, [0058]), map the system memory buffer to the second PCIe device (network interface application 122C stores the packet data 144 received in or otherwise associated with the packets P.sub.input in the shared data structure(s), [0061]), and map the semaphore memory to the second PCIe device (the network interface application 122C, and/or the like) may access the semaphore 140B, [0087]).
While Agostini discloses DMA transfers, Agostini is silent regarding DMA operations by the NIC, therefore does not appear to explicitly disclose “the second PCIe device is to initiate a direct memory access (DMA) transfer to store a copy of the streaming data in memory of the second PCle device without involvement of the CPU.”
However, Amento discloses “the second PCIe device is to initiate a direct memory access (DMA) transfer to store a copy of the streaming data in memory of the second PCle device without involvement of the CPU” (NIC 120 may proceed with the DMA transfer without instruction from the CPU 110, [0028]).
Agostini, Shirizly, and Amento are analogous art because they are from the same field of endeavor, graphics processing systems.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Agostini, Shirizly, and Amento before him or her, to modify the graphics processing system of Agostini in view of Shirizly to include the NIC DMA capabilities of Amento because the technique would reduce CPU operational responsibilities which reduces CPU load.
The suggestion/motivation for doing so would have been to offload transfer handling to the NIC (Shirizly: [0078]).
Therefore, it would have been obvious to combine Agostini, Shirizly, and Amento to obtain the invention as specified in the instant claim.
As to claim 11, the combination of Agostini, Shirizly, and Amento discloses the second PCIe device is to send the streaming data to a client device over a network (Agostini: fig. 1, network 106; Raduchel: a game that is being remotely accessed on the client device 120 and running locally on a virtual machine on the server system, [0047]). The suggestion/motivation to combine remains as indicated above.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Amento in view of Shirizly.
Referring to claim 14, Amento discloses a first Peripheral Component Interconnect Express (PCIe) device (fig. 1, NIC 120) comprising: memory (fig. 1, memory 122); a central processing unit (CPU) (fig. 1, processor 121) operatively coupled to a first interface (fig. 1, transceiver 115), a second interface (fig. 1, host interface 135), and a third interface (fig. 1, transceivers 124), the first interface to couple to a host device (fig. 1, CPU 110), a second interface to couple to a second PCIe device (fig. 1, GPU 130), and the third interface to couple to a network (fig. 1, network links 190); and a hardware synchronization mechanism, wherein the hardware synchronization mechanism is to synchronize streaming data from the second PCIe device to the memory over the second interface (command to the DMA engine of NIC 120 to read from the pinned memory pool of shared memory 132 at GPU…NIC 120 may read out a portion of the pinned memory pool based upon a size of the transfer… copied into NIC memory…in one example, the packet(s) may be loaded into one or more transmit, [0033-0034]), wherein the hardware synchronization mechanism is in the first PCIe device, and wherein the first PCIe device is configured to: (i) poll the semaphore memory to determine when a semaphore value, written by the second PCIe device (GPU setting a polling flag, [0046]), indicates the streaming data is available for transfer (a polling flag…when read, indicates whether or not the packet processing is complete, [0046]), and (ii) initiate transfer of the streaming data in response to the semaphore value (read the polling flag, determine the GPU-based packet processing is completed, and notify the NIC that the processing of at least the first packet is completed (and/or instruct the NIC to read at least the first packet from the memory buffer), [0046]; data that is read via the DMA transfer, [0046]).
While Amento discloses NIC transfer operations “without involvement by the CPU” (NIC 120 may proceed with the DMA transfer without instruction from the CPU 110, [0028]), and polling of a flag (i.e., “a semaphore”) indicating available data, the polling mechanism described in paragraph [0046] appears to indicate involvement of the CPU instead of being “in the first PCIe device” and “without involvement by the host device.”
However, in a similar endeavor of managing network transmissions, Shirizly disclose the polling performed by the NIC (the hardware (e.g., NIC or NIC PE) may perform polling of the hardware interface to see if any new work is available, [0033]), which teaches a polling embodiment being “in the DPU” and “without involvement by the host device.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Amento and Shirizly before him or her, to modify the network system of Amento to include the NIC polling technique of Shirizly because the technique would reduce CPU operational responsibilities which reduces CPU load.
The suggestion/motivation for doing so would have been to offload packet handling to the NIC (Shirizly: [0078]).
Therefore, it would have been obvious to combine Amento and Shirizly to obtain the invention as specified in the instant claim.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Amento in view of Shirizly, as applied to claim 14 above, further in view of Raduchel.
As to claim 15, Amento discloses the first PCIe device is a DPU (fig. 1, NIC 120), and the second PCIe device is a graphics processing unit (GPU) (fig. 1, GPU 130), wherein: the DPU is to initiate a direct memory access (DMA) transfer of a copy of a video bitstream stored in a GPU-mapped system memory buffer to the memory (GPU 130 may allocate the memory pool for use by a DMA engine of NIC 120. In one example, the memory pool is pinned to a PCIe physical memory address. In one example, the pinned memory pool may comprise a shared ring buffer that is readable and writeable by both the NIC 120 and GPU 130, [0022]); perform network operations (NIC 120 may include a plurality of transceivers 124 for sending and receiving data via network links 190, [0017]).
The combination of Amento in view of Shirizly does not appear to explicitly disclose encryption on the video bitstream and an audio bitstream; and send the streaming data to a client device over the network.
However, Raduchel discloses encryption on the video bitstream and an audio bitstream; and send the streaming data to a client device over the network (use encryption protocols in generating the network packet data 204b to be transmitted to the client device, [0076]; applications such as multiplayer games and audio/video conferencing applications, [0120]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Amento, Shirizly, and Raduchel before him or her, to modify the graphics processing system of Amento in view of Shirizly to encryption of streaming data as taught by Raduchel because encryption provides security for data processing and transmission.
The suggestion/motivation for doing so would have been to secure sensitive transmission data (Raduchel: [0141]).
Therefore, it would have been obvious to combine Amento, Shirizly, and Raduchel to obtain the invention as specified in the instant claim.
As to claim 16, the combination of Amento, Shirizly, and Raduchel discloses the DPU further comprises hardware engines and one or more processing cores to perform network operations (Amento: GPU 130 may include a host interface 135, e.g., a PCI or PCIe transceiver (PHY) for communicating with CPU 110 and NIC 120 via bus 180. In addition, GPU 130 may include a plurality of streaming multiprocessors (SMs) 139, a shared memory 132 that is accessible to the plurality of SMs 139, and a scheduler 131 for distributing kernels and data processing assignments to various SMs…core(s) of the SMs 139, performs various routing operations; [0018]) and encryption on the video bitstream and an audio bitstream and send the streaming data to the client device over the network (Raduchel: use encryption protocols in generating the network packet data 204b to be transmitted to the client device, [0076]; applications such as multiplayer games and audio/video conferencing applications, [0120]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Amento, Shirizly, and Raduchel before him or her, to modify the graphics processing system of Amento to encryption as taught by Raduchel because encryption provides security for data processing and transmission.
The suggestion/motivation for doing so would have been to secure sensitive transmission data (Raduchel: [0141]).
Therefore, it would have been obvious to combine Amento, Shirizly, and Raduchel to obtain the invention as specified in the instant claim.
As to claim 17, the combination of Amento, Shirizly, and Raduchel discloses the GPU comprises a GPU encoding engine (Raduchel: GPU chip 310 further includes a rendering module 312 and an encoding module 314, [0078]), the GPU encoding engine to encode the video bitstream and store the encoded bitstream in the GPU-mapped system memory buffer (Amento: shared ring buffer that is readable and writeable by both the NIC 120 and GPU 130, [0022]; Raduchel: a video renderer configured to render the one or more frames of the video data to be transmitted to the client device, (ii) a video encoder configured to encode the one or more rendered frames of the video data, and (iii) graphics memory for temporarily storing the encoded video data, [0020]) and output a completion indication to the semaphore memory (Amento: GPU setting a polling flag…indicates whether or not the packet processing is complete, [0046]).
The suggestion/motivation to combine remains as indicated above.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Amento, Shirizly, and Raduchel, as applied to claims 15-17 above, further in view of Borkovic.
As to claim18, while the combination of Amento, Shirizly, and Raduchel discloses the DPU is to poll the semaphore memory and a DMA transfer of a portion of the video bitstream, the combination is silent regarding the polling scheme and therefore does not appear to explicitly disclose periodically polling and determine a size for a DMA transfer.
However, one of ordinary skill would recognize that periodic polling as one of a finite number of well-known solutions available polling.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Amento, Shirizly, and Raduchel before him or her, to implement the anticipated polling technique according to a periodic polling solution, because the combination demonstrates there was a need to check the semaphore and one of ordinary skill in the art would recognize periodic polling as one of a finite number of predictable solutions for checking a status, with a reasonable expectation of success. The rationale to support a conclusion that the claim would have been obvious is that "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense (MPEP2143.I.E).
Furthermore, Borkovic teaches determine a size for a DMA transfer (data scheduler 750 may determine the size of each set of consecutive DMA transfers; col. 21, lines 55-60).
Amento, Shirizly, Raduchel, and Borkovic are analogous art because they are from the same field of endeavor, direct memory access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Amento, Shirizly, Raduchel, and Borkovic before him or her, to modify the graphics processing system of the combination of Amento, Shirizly, and Raduchel to include the data scheduler of Borkovic in order to manage DMA transfers.
The suggestion/motivation for doing so would have been to optimize data transfers (Borkovic: col. 21, lines 45-60).
Therefore, it would have been obvious to combine Amento, Shirizly, Raduchel, and Borkovic to obtain the invention as specified in the instant claim.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Amento in view of Shirizly, as applied to claim 14 above, further in view of Raduchel.
As to claim 20, Amento discloses the first PCIe device is a graphics processing unit (GPU) (fig. 1, GPU 130),, wherein the second PCIe device is a data processing unit (DPU) (fig. 1, NIC 120).
The combination of Amento in view of Shirizly does not appear to explicitly disclose the DPU is a programmable data center infrastructure on a chip.
However, Raduchel discloses the DPU is a programmable data center infrastructure on a chip (circuit IP blocks, including CPUs, GPUs, NICs…custom low-power system-integrated chips (SoCs)…installed in data centers, [0111]; ).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Amento, Shirizly, and Raduchel before him or her, to substitute the anticipated NIC architecture of Amento with the chip architecture taught by Raduchel because Amento demonstrated the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of some components (step, element, etc.) with other components; Raduchel demonstrated that the substituted components and their functions were known in the art; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable chip architecture.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143.I.B).
Therefore, it would have been obvious to combine Agostini, Shirizly, and Raduchel to obtain the invention as specified in the instant claim.
Allowable Subject Matter
Claims 7 and 12-13 are allowed.
Response to Arguments
Applicant's arguments filed 4/20/2026 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The US Pub. No. 2022/0334989 of Bar-Ilan et al. is pertinent to DPU systems and DMA transfer operations.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC T OBERLY/ Primary Examiner, Art Unit 2184
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