DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 30 June 2026.
Applicant’s election without traverse of Group I in the reply filed on 30 June 2026 is acknowledged. The restriction requirement is deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-8, 10-12 and 14-15 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Loh (US 2024/0297228 A1).
Regarding claim 1, Loh teaches a semiconductor device (Fig. 2) comprising:
a substrate (202);
a 1st source/drain region (220P) above the substrate; and
an under-blocking layer (205; ¶ [0021]: 205 is a leakage block layer ) below the 1st source/drain region,
wherein the under-blocking layer faces the substrate (205 is under 220P and facing 202 along the z-axis), and comprises one or more insulation materials (¶ [0021]: silicon nitride or silicon oxide).
Regarding claim 2, the semiconductor device of claim 1, wherein the under-blocking layer is disposed below a level of a top surface (topmost surface of 202; see Fig. 2) of the substrate.
Regarding claim 5, the semiconductor device of claim 1, wherein the under-blocking layer is configured to prevent or reduce current flow from the 1st source/drain region to the substrate (¶ [0021]: “the p-type source/drain features 220P are spaced apart from the substrate 202 by a leakage block layer 205.. leakage block layer 205 includes a dielectric material” ).
Regarding claim 6, the semiconductor device of claim 1, further comprising:
a channel structure (2080L, see Fig. 2 and ¶ [0021] ) connected to the 1st source/drain region; and
a gate structure (240P; see ¶ [0018] ) configured to control the channel structure (see ¶ [0019]-[0021] ),
wherein a top surface (top surface of 205) of the under-blocking layer is at or below a level of a bottom surface (bottom-most surface of 240P) of the gate structure.
Regarding claim 7, the semiconductor device of claim 1, further comprising:
a channel structure (2080L; Fig. 2) connected to the 1st source/drain region;
a gate structure (240P) configured to control the channel structure (see ¶ [0019]-[0021]); and
an inner spacer (218) between the gate structure and the 1st source/drain region,
wherein the top surface (top surface of 205) of the under-blocking layer is at or below a level of a bottom surface (bottom surface of the bottom-most 218) of the inner spacer.
Regarding claim 8, the semiconductor device of claim 1, further comprising a 2nd source/drain region (220N, see Fig. 2) above the 1st source/drain region.
Regarding claim 10, the 3D-stacked semiconductor device of claim 1, further comprising:
a channel structure (2080L, see Fig. 2) connected to the 1st source/drain region;
a gate structure (240P) configured to control the channel structure (see ¶ [0019]-[0021] ); and
an inner spacer (218) between the gate structure and the 1st source/drain region,
wherein the under-blocking layer and the inner spacer are formed of the same material (silicon oxide or silicon nitride; see ¶ [0018] and ¶ [0021]).
Regarding claim 11, teaches a semiconductor device comprising:
a substrate (202);
a 1st source/drain region (220P) above the substrate; and
an under-blocking layer (205) configured to prevent or reduce current flow (¶ [0021]: leakage current) from the 1st source/drain region to the substrate (¶ [0021]: “the p-type source/drain features 220P are spaced apart from the substrate 202 by a leakage block layer 205.. leakage block layer 205 includes a dielectric material” ) ),
wherein the under-blocking layer comprises one or more insulation materials (¶ [0021]: silicon nitride or silicon oxide).
Regarding claim 12, the semiconductor device of claim 11, wherein the under-blocking layer is disposed below the 1st source/drain region to face the substrate (Fig. 2 shows 205 under 220P and facing 202 along the z-axis).
Regarding claim 14, the semiconductor device of claim 11, wherein the under-blocking layer is formed in the substrate (Fig. 2 shows 205 formed in a cavity of substrate 202).
Regarding claim 15, the semiconductor device of claim 11, further comprising a 2nd source/drain region (220N, see Fig. 2) above the 1st source/drain region.
Claims 1-7 and 9-14 are rejected under 35 USC § 102 (a)(1) and (a)(2) anticipated by Ju (US 2021/0134795 A1).
Regarding claim 1, Ju teaches a semiconductor device (Figs. 3K, 4E, 7-12) comprising:
a substrate (100 & 101A1);
a 1st source/drain (138) region above the substrate; and
an under-blocking layer (137A1) below the 1st source/drain region, wherein the under-blocking layer faces the substrate (see Figures), and comprises one or more insulation materials (¶ [0057]: 134 may be made of carbon-containing silicon nitride; ¶ [0062]: 137A1 is formed from 134).
Regarding claim 2, the semiconductor device of claim 1, wherein the under-blocking layer is disposed below a level (Fig. 3K: bottom-most surface of 137A1 is below the topmost surface of 101A1) of a top surface (topmost surface of 101A1) of the substrate.
Regarding claim 3, the semiconductor device of claim 1, wherein the under-blocking layer comprises:
a 1st portion (middle portion of 137A1 directly under 138; see Fig. 3K) below the 1st source/drain region, vertically overlapping the 1st source/drain region;
a 2nd portion (left portion of 137A1 directly under gate 156A1) at a 1st side (left side of 138) of the 1st source/drain region, not vertically overlapping the 1st source/drain region; and
a 3rd portion (right portion of 137A1 directly under gate 156A2) at a 2nd side (right side of 138) of the 1st source/drain region, not vertically overlapping the 1st source/drain region.
Regarding claim 4, the semiconductor device of claim 3, wherein the 1st portion vertically edges into the substrate such that a length of the 1st portion decreases in a downward direction (downward vertical direction in Figs. 3K, 4E, 7-12) from the 1st source/drain region (the Figures show the middle portion of 137A1 being thicker at the top, i.e., near the gates, and thinner as it goes under the topmost surface of the substrate fin 101A1),
wherein the 2nd portion laterally edges into the substrate such that a thickness (thickness of the leftmost tip of 137A1) of the 2nd portion decreases in a 1st lateral direction (left direction) from the 1st source/drain region, and
wherein the 3rd portion laterally edges into the substrate such that a thickness (thickness of the rightmost tip of 137A1) of the 3rd portion decreases in a 2nd lateral direction (right direction) from the 1st source/drain region.
Regarding claim 5, the semiconductor device of claim 1, wherein the under-blocking layer is configured to prevent or reduce current flow from the 1st source/drain region to the substrate (¶ [0060], [0096] ).
Regarding claim 6, the semiconductor device of claim 1, further comprising:
a channel structure (104b-104d; Fig. 2A; ¶ [0029]) connected to the 1st source/drain region (see Fig. 3K); and
a gate structure (156A1) configured to control the channel structure (¶ [0097]-[0098]),
wherein a top surface (top surface of 137A1) of the under-blocking layer is at or below a level of a bottom surface (bottom surface of 156A1) of the gate structure.
Regarding claim 7, the semiconductor device of claim 1, further comprising:
a channel structure (104b-104d; ¶ [0029]) connected to the 1st source/drain region;
a gate structure (156A1) configured to control the channel structure (¶ [0097]-[0098]); and
an inner spacer (136) between the gate structure and the 1st source/drain region,
wherein a top surface (top surface of 137A1) of the under-blocking layer is at or below a level of a bottom surface (bottommost surface of 136) of the inner spacer.
Regarding claim 9, the semiconductor device of claim 1, wherein the under-blocking layer has a greater length (horizontal length of 137A1) than the 1st source/drain region in a channel-length direction (horizontal direction).
Regarding claim 10, the semiconductor device of claim 1, further comprising:
a channel structure (104b-104d) connected to the 1st source/drain region;
a gate structure (156A1) configured to control the channel structure (¶ [0097]-[0098]); and
an inner spacer (136) between the gate structure and the 1st source/drain region,
wherein the under-blocking layer and the inner spacer are formed of the same material (¶ [0059] ).
Regarding claim 11, Ju teaches a semiconductor device (Figs. 3K, 4E, 7-12) comprising:
a substrate (100 & 101A1) ;
a 1st source/drain region (138) above the substrate; and
an under-blocking layer (137A1) configured to prevent or reduce current flow from the 1st source/drain region to the substrate (¶ [0060], [0096]),
wherein the under-blocking layer comprises one or more insulation materials (¶ [0057]: 134 may be made of carbon-containing silicon nitride; ¶ [0062]: 137A1 is formed from 134).
Regarding claim 12, the semiconductor device of claim 11, wherein the under-blocking layer is disposed below the 1st source/drain region to face the substrate (Figs. 3K, 4E, 7-12 show 137A1 below 138 and facing 100)
Regarding claim 13, the semiconductor device of claim 11, wherein the under-blocking layer comprises:
a 1st portion (middle portion of 137A1 directly under 138) below the 1st source/drain region, vertically overlapping the 1st source/drain region;
a 2nd portion (left portion of 137A1 directly under gate 156A1) at a 1st side (left side of 138) of the 1st source/drain region, not vertically overlapping the 1st source/drain region; and
a 3rd portion (right portion of 137A1 directly under gate 156A2) at a 2nd side (right side of 138) of the 1st source/drain region, not vertically overlapping the 1st source/drain region.
Regarding claim 14, the semiconductor device of claim 11, wherein the under-blocking layer is formed in the substrate (Fig. 3C shows recess 130 formed in the substrate 100; Fig. 3E shows 134 formed in the recess; Fig. 3F shows 137A1 formed from 134).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Liao (US 2021/0366907 A1) Fig. 17B also shows an under-blocking layer (214 & 282 & 276) in between a first source/drain (228D) and a substrate (290).
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
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