Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9-10, 12-13, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jan et al. (Pub. No. US 20190287973 A1), hereinafter referred to as Jan, in view of Seo et al. (Pub. No. US 20220037236 A1), hereinafter referred to as Seo.
Regarding claim 1, Jan teaches a semiconductor device comprising: an active region extending in a first direction and including first conductivity-type impurities (Figs. 2A&B, fins 201, 202, substrate 205, substrate surface layer 206; ¶28-30); an ion doped region in the active region and extending in the first direction, wherein the ion doped region includes second conductivity-type impurities (Fig. 2B, lower sub-fin region 210A,210B; ¶31); a gate structure extending in a second direction, the second direction intersecting the first direction, wherein the gate structure is disposed on the active region and traverses the active region (Figs. 2A&B, gate stack 260; ¶30); a source/drain region on the active region on at least one side of the gate structure (Fig. 2C, source/drain contacts 255; ¶30); and a device isolation layer surrounding the active region (Figs. 2A&B, isolation dielectric 208; ¶28). However, Jan does not explicitly teach an interlayer insulating layer on the device isolation layer and covering the gate structure and the source/drain region; a vertical power structure extending in a third direction, the third direction perpendicular to the first and second directions, wherein the vertical power structure passes through the device isolation layer and the interlayer insulating layer; and a bottom wiring connected to the vertical power structure and contacting a bottom surface of the active region.
Seo teaches an interlayer insulating layer on the device isolation layer and covering the gate structure and the source/drain region (Fig. 20C, first interlayer insulating layer 110, second interlayer insulating layer 120, device isolation layer ST; ¶78-80, 100-105); a vertical power structure extending in a third direction, the third direction perpendicular to the first and second directions, wherein the vertical power structure passes through the device isolation layer and the interlayer insulating layer (Fig. 20C, penetration via structure 200; ¶100-105); and a bottom wiring connected to the vertical power structure and contacting a bottom surface of the active region (Fig. 20C, power delivery network 150; ¶49-50, 100-105).
Jan and Seo are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jan with the teachings of Seo such that the device has an interlayer insulating layer on the device isolation layer and covering the gate structure and the source/drain region; a vertical power structure extending in a third direction, the third direction perpendicular to the first and second directions, wherein the vertical power structure passes through the device isolation layer and the interlayer insulating layer; and a bottom wiring connected to the vertical power structure and contacting a bottom surface of the active region. For the purpose of having a device with a backside power delivery network which has benefits such as creating smaller devices with increased reliability, as recognized by Seo.
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Regarding claim 2, Jan further teaches the ion doped region is separated from a top surface and the bottom surface of the active region (Fig. 2B, lower sub-fin region 210A,210B, substrate 205, surface layer 206, fins 201,202; ¶28-32).
Regarding claim 3, Jan further teaches a distance at which the ion doped region is separated from the top surface of the active region is greater than a distance at which the ion doped region is separated from the bottom surface of the active region (Fig. 2B, thickness of substrate surface layer 206 (Ts), heights H1, H2, H3; ¶30-40).
Regarding claim 4, Jan further teaches the first conductivity-type impurities have a first conductivity-type, and the second conductivity-type impurities have a second conductivity-type, the first conductivity-type is P-type, the second conductivity-type is N-type, and the second conductivity-type impurities include at least one of phosphorus (P), arsenic (As), and antimony (Sb) (fins 201,202, substrate 205, lower sub-fin region 210A,210B; ¶28-31).
Regarding claim 5, Jan further teaches the first conductivity-type impurities have a first conductivity-type, and the second conductivity-type impurities have a second conductivity-type, the first conductivity-type is N-type, the second conductivity-type is P-type, and the second conductivity-type impurities include at least one of boron (B), aluminum (Al), gallium (Ga), and indium (In) (fins 201,202, substrate 205, lower sub-fin region 210A,210B; ¶28-31).
Regarding claim 6, Jan further teaches a top end of the ion doped region is lower than a top surface of the device isolation layer (Fig. 2B, lower sub-fin region 210A,210B, isolation dielectric 208; ¶28-40). However, Jan does not explicitly teach a top end of the ion doped region is lower than an interface between the device isolation layer and the interlayer insulating layer. Seo teaches an interlayer insulating layer on the device isolation layer and covering the gate structure and the source/drain region (Fig. 20C, first interlayer insulating layer 110, second interlayer insulating layer 120, device isolation layer ST; ¶78-80, 100-105).
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jan with the teachings of Seo such that the top end of the ion doped region is lower than an interface between the device isolation layer and the interlayer insulating layer. For the purpose of including an interlayer insulating layer to prevent undesired electrical connections and protect the gate structure and the source/drain region.
Regarding claim 7, Jan further teaches an expanded ion doped region in contact with the ion doped region in the active region, the expanded ion doped region including the first conductivity-type impurities (Fig. 2B, upper sub-fin region 230A,230B; ¶37).
Regarding claim 9, Jan further teaches the expanded ion doped region is separated from a top surface and the bottom surface of the active region (Fig. 2B, upper sub-fin region 230A,230B, substrate 205, surface layer 206, fins 201,202; ¶28-40).
Regarding claim 10, Jan further teaches a distance at which the expanded ion doped region is separated from the top surface of the active region is greater than a distance at which the expanded ion doped region is separated from the bottom surface of the active region (Fig. 2B, thickness of substrate surface layer 206 (Ts), heights H1, H2, H3; ¶30-40).
Regarding claim 12, Jan teaches a semiconductor device comprising: an active region extending in a first direction and including first impurities having a first conductivity-type (Figs. 2A&B, fins 201, 202, substrate 205, substrate surface layer 206; ¶28-30); an ion doped region located in the active region and including second impurities (Fig. 2B, lower sub-fin region 210A,210B; ¶31); a gate structure extending in a second direction, the second direction intersecting the first direction, wherein the gate structure is disposed on the active region and traverses the active region (Figs. 2A&B, gate stack 260; ¶30); ); a source/drain region on the active region on at least one side of the gate structure (Fig. 2C, source/drain contacts 255; ¶30); and a device isolation layer surrounding the active region (Figs. 2A&B, isolation dielectric 208; ¶28). However, Jan does not explicitly teach an interlayer insulating layer on the device isolation layer and covering the gate structure and the source/drain region; a vertical power structure extending in a third direction, the third direction perpendicular to the first and second directions, wherein the vertical power structure passes through the device isolation layer and the interlayer insulating layer; and a bottom wiring contacting a bottom surface of the vertical power structure and electrically connected to the vertical power structure.
Seo teaches an interlayer insulating layer on the device isolation layer and covering the gate structure and the source/drain region (Fig. 20C, first interlayer insulating layer 110, second interlayer insulating layer 120, device isolation layer ST; ¶78-80, 100-105); a vertical power structure extending in a third direction, the third direction perpendicular to the first and second directions, wherein the vertical power structure passes through the device isolation layer and the interlayer insulating layer (Fig. 20C, penetration via structure 200; ¶100-105); and a bottom wiring contacting a bottom surface of the vertical power structure and electrically connected to the vertical power structure (Fig. 20C, power delivery network 150, penetration via structure 200; ¶49-50, 100-105).
Jan and Seo are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jan with the teachings of Seo such that an interlayer insulating layer on the device isolation layer and covering the gate structure and the source/drain region; a vertical power structure extending in a third direction, the third direction perpendicular to the first and second directions, wherein the vertical power structure passes through the device isolation layer and the interlayer insulating layer; and a bottom wiring contacting a bottom surface of the vertical power structure and electrically connected to the vertical power structure. For the purpose of having a device with a backside power delivery network which has benefits such as creating smaller devices with increased reliability, as recognized by Seo.
Regarding claim 13, Jan further teaches the ion doped region is an insulating region (Fig. 2B, lower sub-fin region 210A,210B, upper sub-fin region 230A,230B; ¶26, 37, 40).
Regarding claim 17, Jan further teaches the second impurities have a second conductivity-type (Fig. 2B, lower sub-fin region 210A,210B; ¶31).
Regarding claim 18, Jan teaches a semiconductor device comprising: an active region extending in a first direction and including first impurities (Figs. 2A&B, fins 201, 202, substrate 205, substrate surface layer 206; ¶28-30); an ion doped region located in the active region and including second impurities (Fig. 2B, lower sub-fin region 210A,210B; ¶31); a gate structure extending in a second direction, the second direction intersecting the first direction, wherein the gate structure is disposed on the active region and traverses the active region (Figs. 2A&B, gate stack 260; ¶30); and a source/drain region on the active region on at least one side of the gate structure (Fig. 2C, source/drain contacts 255; ¶30). However, Jan does not explicitly teach a vertical power structure extending in a third direction, the third direction perpendicular to the first and second directions, wherein the vertical power structure is electrically connected to the source/drain region; and a bottom wiring disposed below the vertical power structure and electrically connected to the vertical power structure.
Seo teaches a vertical power structure extending in a third direction, the third direction perpendicular to the first and second directions, wherein the vertical power structure is electrically connected to the source/drain region (Fig. 20C, penetration via structure 200, source/drain region SD; ¶41, 44, 100-105); and a bottom wiring disposed below the vertical power structure and electrically connected to the vertical power structure (Fig. 20C, power delivery network 150, penetration via structure 200; ¶49-50, 100-105).
Jan and Seo are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jan with the teachings of Seo such that a vertical power structure extending in a third direction, the third direction perpendicular to the first and second directions, wherein the vertical power structure is electrically connected to the source/drain region; and a bottom wiring disposed below the vertical power structure and electrically connected to the vertical power structure. For the purpose of having a device with a backside power delivery network which has benefits such as creating smaller devices with increased reliability, as recognized by Seo.
Regarding claim 19, Jan further teaches the first impurities have a first conductivity-type, and the second impurities have a second conductivity-type (Figs. 2A&B, fins 201, 202, substrate 205, substrate surface layer 206, lower sub-fin region 210A,210B; ¶28-31).
Regarding claim 20, Jan further teaches the ion doped region is an insulating region (Fig. 2B, lower sub-fin region 210A,210B, upper sub-fin region 230A,230B; ¶26, 37, 40)
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jan in view of Seo as applied to claim 13 above, and further in view of Wu et al. (US Patent No. 9,947,658), hereinafter referred to as Wu.
Regarding claim 14, Jan in view of Seo does not explicitly teach the second impurities include at least one of carbon (C), oxygen (O), and nitrogen (N).
Wu teaches the second impurities include at least one of carbon (C), oxygen (O), and nitrogen (N) (Fig. 13, well region 1265; Col. 6, lines 58-63).
Jan, Seo, and Wu are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jan in view of Seo with the teachings of Wu such that the second impurities include at least one of carbon (C), oxygen (O), and nitrogen (N). For the purpose of optimizing the electrical properties of the device such as preventing current leakage and preventing back diffusion, as recognized by Wu.
Regarding claim 15, Jan further teaches the ion doped region is disposed at a bottom end of the active region (Fig. 2B, thickness of substrate surface layer 206 (Ts), heights H1, H2, H3; ¶30-40).
Regarding claim 16, Jan teaches an ion doped region (Fig. 2B, lower sub-fin region 210A,210B; ¶31). However, Jan does not explicitly teach the bottom wiring contacting the ion doped region.
Seo teaches bottom wiring (Fig. 20C, power delivery network 150; ¶49-50, 100-105).
Jan and Seo are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jan with the teachings of Seo such that the bottom wiring contacts the ion doped region. For the purpose of having a device with a backside power delivery network which has benefits such as creating smaller devices with increased reliability, as recognized by Seo.
Claim(s) 8 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jan in view of Seo as applied to claims 1 and 7 above, and further in view of Jang et al. (Pub. No. US 20200220015 A1), hereinafter referred to as Jang.
Regarding claim 8, Jan in view of Seo does not explicitly teach a concentration of the first conductivity-type impurities in the expanded ion doped region is higher than a concentration of the first conductivity-type impurities in the active region.
Jang teaches a concentration of the first conductivity-type impurities in the expanded ion doped region is higher than a concentration of the first conductivity-type impurities in the active region (Figs. 3A&B, doping regions 105D, first epitaxial layer 152, second epitaxial layer 154 ¶6, 26, 31, 32).
Jan, Seo, and Jang are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jan in view of Seo with the teachings of Jang such that a concentration of the first conductivity-type impurities in the expanded ion doped region is higher than a concentration of the first conductivity-type impurities in the active region. For the purpose of optimizing the electrical properties of the device and preventing undesired ion diffusion.
Regarding claim 11, Jan in view of Seo does not explicitly teach a plurality of channel layers separated in the third direction on the active region and surrounded by the gate structure.
Jang teaches a plurality of channel layers separated in the third direction on the active region and surrounded by the gate structure (Figs. 7 & 8, channel structures 140, active region 105, gate structures 160a; ¶77-79).
Jan, Seo, and Jang are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jan in view of Seo with the teachings of Jang such that the device has a plurality of channel layers separated in the third direction on the active region and surrounded by the gate structure. For the purpose of having a device that is a gate-all-around type field effect transistor, as recognized by Jang.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./ Examiner, Art Unit 2897
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