DETAILED ACTION
This action is responsive to the amendment received on 07/02/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in REPUBLIC OF KOREA on 08/16/2023.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 21-23, 26, and 28-31 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 has been amended to recite the following limitation:
“a first wafer including a first substrate, a first device layer disposed over the first substrate, and a first bonding layer disposed over the first device layer; and
a second wafer including a second substrate, a second device layer disposed over the second substrate and a second bonding layer disposed over the second device layer to be attached to the first bonding layer using hybrid bonding”
This limitation is unclear in view of the specification and drawings. Both wafers individually require the layers stacked in a vertical direction wherein the device layers are over the substrates and the bonding layers are over the device layers. However, the claim further requires the bonding layers be bonded together using hybrid bonding, i.e. the top layers of each wafer are hybrid bonded to one another. This is believed by the examiner to be shown in Figures 10-12 of the instant application where bonding layers #250 and #260 are hybrid bonded to one another (see [00109]). In all of figures 10-12, the device layer (#DL1) of the upper wafer (#W1) is no longer over the substrate (#T-sub1) and the bonding layer (#250) of the upper wafer (#W1) is no longer over the device layers (#DL1) as the device is inverted to be bonded. Rotating it would create a similar problem for the lower wafer (#W2). It is therefore unclear if the claim is to the order of stacking of a device still in progress (i.e. the claim covers prior to the bonding taking place) which is eventually going to be bonded (based on the language of “to be attached”) or is simply describing the order of stacking prior to bonding but the claim is to the stacked device wherein the layers are no longer over one another as required (preamble of claim refers to a singular stack type semiconductor device). Therefore, claim(s) 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 22-23, 26, and 28-31 are rejected under 35 U.S.C. 112(b) at least for their dependencies.
For the purposes of this examination, it will be interpreted that the claim is to the final stacked device wherein the layers are no longer over one another as required but could be interpreted as having been stacked that way prior to bonding.
Claim 26 has been amended to recite “wherein the second device layer includes a plurality of second conductive patterns electrically connected to at least one of the plurality of second conductive patterns” in the final two lines of the claim. It unclear if applicant is describing an element being electrically connected to itself which is a redundant/unclear claim limitation or if applicant’s intention was to describe the second conductive patterns as being electrically connected to a different structure, such as the second conductive structures, and this was a typo. It may be that the claim 26 amendments were intended to be similar to the amendments to claim 23 for the first conductive patterns and first conductive structures. Therefore, claim(s) 26 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 28 and 29 are rejected under 35 U.S.C. 112(b) at least for their dependencies.
For the purposes of this examination, it will be interpreted that the claim reads as “wherein the second device layer includes a plurality of second conductive patterns electrically connected to at least one of the plurality of second conductive structures”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-7, 21-23, 26, and 28-31 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0301408 A1; Uchiyama, Shiro; 10/2018; (“Uchiyama”).
Regarding Claim 1. Uchiyama discloses A wafer (Figures 1A-1C and 2, where Figure 2 shows the plurality of chips on a wafer and Figures 1A-1C show sections of one of the chips) comprising:
a substrate (#100, Figure 1C, semiconductor substrate) including a first surface (#100U, Figure 1C, upper surface) and a second surface (#100L, Figure 1C, lower surface) opposite to each other (Figure 1C, #100U and #100L are opposite each other);
a plurality of conductive structures (#127s, Figure 1C, conductive portions) formed through the substrate (Figure 1C, #127s are formed at least partially through #100), the plurality of conductive structures insulated from the substrate (Figure 1C, #127s are insulated from #100 by #108s which are TDV-STI (through dielectric via – shallow trench isolation) regions);
a polishing stop layer (#107s and #109s, Figure 1C, STI (shallow trench isolation) regions of #106 (first dielectric film) which may function as a polishing stop layer according to [0048]) formed in a selected portion of the substrate (Figure 1C, #107s and #109s are formed in selected portions of #100), the polishing stop layer including one or more insulation trenches each filled with an insulation material (#107 and #109, Figure 1C, STI regions are a plurality of trenches filled with the dielectric material of #106) and having a depth corresponding to a thickness of the substrate (Figure 1C, #107s and #109s are observed to have the thickness #d1 of the substrate #100) and depths of the plurality of conductive structures (Figure 1C, #107s and #109s have a depth in the substrate which corresponds to a depth of #127s in the substrate, i.e. both extend fully through #100); and
a device layer (#121B, Figure 1C, interconnect layer comprising portions of a plurality of devices such as transistors #116 and #117) supported by the substrate (Figure 1C, #121B is supported at least partially by #100) and structured to include a plurality of conductive patterns (#118b, Figure 1C, contact vias) configured to electrically connect to at least one of the plurality of conductive structures (Figure 1C, the plurality of #118bs overlapping with #127s are electrically connected to the #127s though TDV pads #119 and barrier portions #126),
wherein at least one of the plurality of conductive structures is spaced apart from the polishing stop layer (Figure 1C, #127s are spaced apart from #107s and #109s by at least #126s).
Regarding Claim 3. Uchiyama discloses The wafer of claim 1, wherein a portion of the substrate is interposed between the at least one of the plurality of conductive structures and the polishing stop layer adjacent to the at least one of the plurality of conductive structures (Figure 1C, each #127 and its adjacent #107s/#109s are interposed by portions of #100 therebetween).
Regarding Claim 4. Uchiyama discloses The wafer of claim 1, wherein the polishing stop layer has a grid shape partition the plurality of conductive structures into individual conductive structures (Figures 1A-1C, #109 has a grid or lattice shape which partitions the plurality of #127s into individual conductive structures when viewed from the top down).
Regarding Claim 5. Uchiyama discloses The wafer of claim 1, wherein the substrate comprises a plurality of die regions and a scribe lane for defining the plurality of die regions (Figure 2, the wafer comprises a plurality of die regions (#20, chips) which are partitioned by lanes for cutting the chips, also known as scribe layers, according to [0036]), and the selected portion of the substrate includes at least one of the die regions or the scribe lane (Figures 1A-1C and 2, the polishing stop layer portions #109 are formed in at least the regions of the plurality of die regions).
Regarding Claim 6. Uchiyama discloses The wafer of claim 1, wherein the device layer (#121B) comprises a memory component (#113, Figure 1C, memory cell transistor which is at least partially included in #121B) and at least one of a logic component or a driver component (#116, Figure 1C, peripheral transistor which is a logic device in the peripheral region of #121B), the substrate comprises a pattern concentration region corresponding to the memory component (#PR, Figure 1C annotated below, region where #113 is located) and a dummy region corresponding to the at least one logic component or the driver component (#DR, Figure 1C annotated below, region where #116 is located), and the selected portion of the substrate includes the pattern concentration region or the dummy region (Figure 1C annotated, the selected portion of #100 where #109s are formed includes the dummy region), and
wherein a size of the polishing stop layer positioned in the pattern concentration region is smaller than a size of the polishing stop layer positioned in the dummy region (Figure 1C, the lateral size of #107s in the #PR region is smaller than the lateral size of the #109s in the #DR region, i.e. #107s are narrower than #109s in Figure 1C).
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Regarding Claim 7. Uchiyama discloses The wafer of claim 1, further comprising an isolation layer (#108, Figure 1C, TDV-STI regions) formed in the substrate from the first surface of the substrate (Figure 1C, #108s are formed from the upper surface #100U of #100), the isolation layer having a depth shallower than a depth of the polishing stop layer (Figure 1C, #108s have a tapered shape such that their lateral edges have depths which are shallower than central depths of #107s and #109s which are formed to the full depth of #100, examiner notes that “a depth” does not require reference specifically to a greatest or maximum depth).
Regarding Claim 21. Uchiyama discloses A stack type semiconductor device (#2000, Figure 12, stacked layers of a semiconductor device) comprising:
a first wafer (#30, Figure 12, layer which may be a chip #20 from Figure 5 according to [0052], Figure 1C shows also shows the device of Figure 5 after the substrate #100 has been thinned as in Figure 12, Figure 1C may be referenced for certain element numbers) including a first substrate (#100, Figure 5, substrate of #30 which is not numbered in Figure 12), a first device layer disposed over the first substrate (#121B, Figure 5, interconnect layer of #30 disposed over #100 in Figure 5) and a first bonding layer (#121C, Figure 5, contact bump layer of #30 which is not numbered in Figure 12) disposed over the first device layer (Figures 5 and 12, #121C is disposed over #121B of #30 in Figure 5); and
a second wafer (#30’, Figure 12, layer which may be a chip #20 from Figure 5 according to [0052], Figure 1C shows also shows the device of Figure 5 after the substrate #100 has been thinned as in Figure 12, Figure 1C may be referenced for certain element numbers) including a second substrate (#100, Figure 5, substrate of #30’ which is not numbered in Figure 12), a second device layer disposed over the second substrate (#121B, Figure 5, interconnect layer of #30’ disposed over #100 in Figure 5) and a second bonding layer (#121C, Figure 5, contact bump layer of #30’ which is not numbered in Figure 12) disposed over the second device (Figures 5 and 12, #121C is disposed over #121B of #30’ in Figure 5) to be attached to the first bonding layer using hybrid-bonding (Figures 5 and 12, the layers #121C of #30 and #30’ are interpreted as hybrid bonding through the hybrid connections of their respective dielectric layers (#122, interlayer dielectric films) and their respective metal contact bumps (#123, copper contact bumps, [0035])),
wherein the first substrate includes a plurality of first polishing stop layers (#107s and #109s, Figure 5, STI (shallow trench isolation) regions of #106 (first dielectric film) of #30 which may function as a polishing stop layer according to [0048], not numbered in Figure 12) and a plurality of first conductive structures (#127s, Figures 1C and 12, conductive portions of #30) insulated from the first substrate (Figures 1C and 12, #127s are insulated from #100 of #30 by #108s which are TDV-STI (through dielectric via – shallow trench isolation), each of the first polishing stop layers includes one or more insulation trench structures that are filled with an insulation material (#107s and #109s, Figures 5 and 12, STI regions are a plurality of trenches filled with the dielectric material of #106) and have a depth corresponding to a thickness of the first substrate (Figure 12, #107s and #109s are observed to have the thickness of the substrate #100 of #30) and depths of the plurality of first conductive structures (Figures 1C and 12, #107s and #109s have a depth in the substrate of #30 which corresponds to a depth of #127s in the substrate, i.e. both extend fully through #100),
wherein a portion of the first substrate is interposed between at least one of the plurality of first conductive structures and an adjacent on of the plurality of first polishing stop layers (Figures 1C and 12, #127s are spaced from #107s and #109s by portions of #100 of #30 interposed between them).
Regarding Claim 22. Uchiyama discloses The stack type semiconductor device of claim 21,
wherein the first bonding layer comprises a plurality of first bonding pads (#123, Figures 5 and 12, contact bumps of #30 and not numbered in Figure 12) connected to interconnection layers of the first device layer (#118 of #121B, Figures 5 and 12, wirings for contact plugs of the interconnect layer which are connected to the bonding pads #123, all of #30 and not numbered in Figure 12) and a first bonding insulation layer (#122, Figures 5 and 12, interlayer dielectric film of #30 not numbered in Figure 12) positioned between the first bonding pads (Figures 5 and 12, #122 is located between adjacent #123s in #30), and
wherein the second bonding layer comprises a plurality of second bonding pads (#123, Figures 5 and 12, contact bumps of #30’ and not numbered in Figure 12) in contact with the first bonding pads (Figure 12, the contact bumps of #30 and #30’ are in direct contact with each other) and a second bonding insulation layer (#122, Figures 5 and 12, interlayer dielectric film of #30’ not numbered in Figure 12) positioned between the second bonding pads (Figures 5 and 12, #122 is located between adjacent #123s in #30’).
Regarding Claim 23. Uchiyama discloses The stack type semiconductor device of claim 21,
wherein the first device layer includes a plurality of first conductive patterns (#118b, Figures 1C, 5, and 12, contact vias of #30) configured to electrically connect to at least one of the plurality of first conductive structures (Figures 1C, 5, and 12, the plurality of #118bs overlapping with #127s are electrically connected to the #127s though TDV pads #119 and barrier portions #126).
Regarding Claim 26. Uchiyama discloses The stack type semiconductor device of claim 23, wherein the second substrate comprises a plurality of second polishing stop layers (#107 and #109 of #30’, Figure 5, STI regions of #106 of #30’ which is a dielectric film according to [0029] which may function as a polishing stop layer according to [0048]; not numbered in Figure 12) and a plurality of second conductive structures (#127s, Figures 1C, 5, and 12, conductive portions of #30’) insulated from the second substrate (Figures 1C and 12, #127s are insulated from #100 of #30’ by #108s which are TDV-STI (through dielectric via – shallow trench isolation), each of the second polishing stop layers has a depth corresponding to a thickness of the second substrate (Figure 12, #107s and #109s are observed to have the thickness of the substrate #100 of #30’) and depths of the plurality of second conductive structures (Figures 1C and 12, #107s and #109s have a depth in the substrate of #30’ which corresponds to a depth of #127s in the substrate, i.e. both extend fully through #100), and
wherein the second device layer includes a plurality of second conductive patterns (#118b, Figures 1C, 5, and 12, contact vias of #30’) electrically connected to at least one of the plurality of second conductive structures (Figures 1C, 5, and 12, the plurality of #118bs overlapping with #127s are electrically connected to the #127s though TDV pads #119 and barrier portions #126 in #30’).
Regarding Claim 28. Uchiyama discloses The stack type semiconductor device of claim 26, wherein the second device layer comprises a second memory component (#113, Figures 1C and 12, memory cell transistor which is at least partially included in #121B of #30’) and at least one of a second logic component or a second driver component (#116, Figure 1C and 12, peripheral transistor which is a logic device in the peripheral region of #121B of #30’), the second substrate comprises a second pattern concentration region corresponding to the second memory component (#PR, Figure 1C annotated above, region where #113 is located) and a second dummy region corresponding to the at least one of the second logic component or the second driver component (#DR, Figure 1C annotated above, region where #116 is located), and
wherein each of the second polishing stop layers in the second pattern concentration region has a size smaller than that of each of the second polishing stop layers in the second dummy region (Figures 1C, 5, and 12, the lateral size of each #107s in the #PR region is smaller than the lateral size of each #109s in the #DR region, i.e. #107s are narrower than #109s in Figure 1C).
Regarding Claim 29. Uchiyama discloses The stack type semiconductor device of claim 26, wherein at least one of the second polishing stop layers is positioned between adjacent second conductive structures (Figures 1C, 5 and 12, at least one #109 is positioned between adjacent #127s in #30’).
Regarding Claim 30. Uchiyama discloses The stack type semiconductor device of claim 21, wherein the first device layer comprises a first memory component (#113, Figures 1C and 12, memory cell transistor which is at least partially included in #121B of #30) and at least one of a first logic component or a first driver component (#116, Figures 1C and 12, peripheral transistor which is a logic device in the peripheral region of #121B of #30), the first substrate comprises a first pattern concentration region corresponding to the first memory component (#PR, Figure 1C annotated above, region where #113 is located) and a first dummy region corresponding to the at least one of the first logic component or the first driver component (#DR, Figure 1C annotated above, region where #116 is located), and
wherein each of the first polishing stop layers in the first pattern concentration region has a size smaller than that of each of the first polishing stop layers in the first dummy region (Figures 1C, 5, and 12, the lateral size of each #107s in the #PR region is smaller than the lateral size of each #109s in the #DR region, i.e. #107s are narrower than #109s in Figure 1C).
Regarding Claim 31. Uchiyama discloses The stack type semiconductor device of claim 21, wherein at least one of the first polishing stop layers is positioned between adjacent first conductive structures (Figures 1C, 5 and 12, at least one #109 is positioned between adjacent #127s in #30).
Response to Arguments/Amendments
Applicant’s amendments to claims 5 and 21 along with corresponding remarks, see page 6 of the remarks, filed 07/02/2026, with respect to the objections to claims 5 and 22 have been fully considered. The objections to claims 5 and 22 have been withdrawn.
Applicant’s amendments to claim 1 and corresponding arguments, see pages 6-9 of the remarks, filed 07/02/2026, with respect to the 35 U.S.C. 102 rejection of claim 1 and its corresponding dependent claims have been fully considered but have not been found persuasive. Claims 1 and 3-7 stand rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0301408 A1; Uchiyama, Shiro; 10/2018; (“Uchiyama”).
Applicant first argues that Uchiyama does not disclose “a polishing stop layer formed in a selected portion of the substrate, the polishing stop layer including one or more insulation trenches each filled with an insulation material and having a depth corresponding to a thickness of the substrate and depths of the plurality of conductive structures” as recited in amended in claim 1. In particular, applicant argues on pages 7-8 of the remarks that the STI dielectric film (#106) of Uchiyama which makes up elements #107 and #109 does not read on a polishing stop layer because [0048] of Uchiyama does not characterize the individual layers as controlling polishing characteristics.
Examiner respectfully disagrees. [0048] of Uchiyama states “applying back grinding (BG) and chemical mechanical planarization (CMP) to the lower surface 200L, until exposing a rear surface 206L of a first dielectric film (STI dielectric film) 206. Polishing may be stopped by endpoint detection of the first dielectric film (STI dielectric film) 206 when the rear surface 206L of the first dielectric film (STI dielectric film) 206 is reached” (emphasis added) and is in reference to Figure 7 of the method of making. Examiner notes that in Figure 7, each element number has been increased by 100 (i.e. #106 = #206, STI dielectric film). Figure 7 clearly shows all the portions of #106/#206 acting as a polishing stop layer by halting the thinning of the substrate such that all of their upper surfaces are exposed at the stopping point.
Applicant second argues that Uchiyama fails to disclose the limitation of “at least one of the plurality of conductive structures is spaced apart from the polishing stop layer”, stating in particular on page 9 of the remarks that each of the conductive structures are interpreted as immediately adjacent to the polishing stop layer.
Examiner respectfully disagrees. There are a number of interpretations by which Uchiyama may be interpreted to read on this claim limitation. In Figure 1C, several of the originally interpreted conductive structures (#114, source/drain regions) are observed to be spaced apart from adjacent portions of #106 by portions of #100. See for example the #114 circled in the annotation below. In response to other amendments made to the claim, element #127 may be interpreted as the “conductive structure” which is spaced apart from the adjacent portions of #107 and #109 at least by the barrier layer #126. For these reasons, it is the examiner’s interpretation that Uchiyama does teach this limitation.
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The dependent claims have further not been found allowable for their dependence on claim 1 as suggested on page 9 of the remarks. Claims 1 and 3-7 stand rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0301408 A1; Uchiyama, Shiro; 10/2018; (“Uchiyama”).
Applicant’s amendments to claim 21 and corresponding arguments, see pages 9 of the remarks, filed 07/02/2026, with respect to the 35 U.S.C. 102 rejection of claim 21 and its corresponding dependent claims have been fully considered but have not been found persuasive. Claims 21-23, 26, and 28-31 stand rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0301408 A1; Uchiyama, Shiro; 10/2018; (“Uchiyama”).
Applicant argues on page 9 of the remarks that claim 21 is allowable for at least the same reasons as claim 1. The arguments regarding claim 1 were not found persuasive for the reasons provided above. In particular applicant argues on page 9 that Uchiyama does not disclose “a first portion of the first substrate is interposed between at least one of the plurality of first conductive structures and an adjacent one of the plurality of first polishing stop layers” since they are interpreted by the applicant as immediately adjacent.
Examiner respectfully disagrees. There are a number of interpretations by which Uchiyama may be interpreted to read on this claim limitation. In Figure 1C, several of the originally interpreted conductive structures (#114, source/drain regions) are observed to be spaced apart from adjacent portions of #106 by portions of #100. See for example the #114 circled in the annotation above. In response to other amendments made to the claim, element #127 may be interpreted as the “conductive structure” which is spaced apart from the adjacent portions of #107 and #109 by the barrier layer #126 and portions of #100. For these reasons, it is the examiner’s interpretation that Uchiyama does teach this limitation.
The dependent claims have further not been found allowable for their dependence on claim 21 as suggested on page 9 of the remarks. Claims 21-23, 26, and 28-31 stand rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0301408 A1; Uchiyama, Shiro; 10/2018; (“Uchiyama”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE KIM can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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