Prosecution Insights
Last updated: July 17, 2026
Application No. 18/434,625

JET IMPINGEMENT COOLING FOR HIGH POWER SEMICONDUCTOR DEVICES USING MONOLITHIC MICROSTRUCTURES

Non-Final OA §102
Filed
Feb 06, 2024
Examiner
NIEVES, NELSON J
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Components Industries LLC
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
605 granted / 803 resolved
+7.3% vs TC avg
Strong +16% interview lift
Without
With
+16.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
23 currently pending
Career history
823
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
72.1%
+32.1% vs TC avg
§102
5.6%
-34.4% vs TC avg
§112
21.4%
-18.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 803 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-8, 13-16, 18, 21-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bhunia (US 20130032311), hereinafter referred to as Bhunia. Re claim 1, 13 and 21, Bhunia teaches a jet impingement cooling assembly for semiconductor devices, comprising: an inlet chamber (e.g. 215) configured to receive an inlet fluid flow; a jet plate (e.g. 220) having at least one jet nozzle (e.g. ¶ 20, “The jet head 220 has a plurality of micro-jet regions 230 that each have one or more nozzles”) formed therein and coupled to the inlet chamber (see Fig 2), and positioned to direct the inlet fluid flow from the inlet chamber through the at least one jet nozzle to provide an impinging fluid flow (Fig 2); a heat exchange base (200) configured to receive at least one semiconductor device (115) with a frontside facing away from the inlet chamber and a backside facing the jet plate (see Fig 2); an impingement layer (e.g. 225) positioned between the at least one jet nozzle and the backside of the at least one semiconductor device to receive the impinging fluid flow, the impingement layer having impingement surface structures (110) formed thereon; and an outlet chamber (chamber in 215 facilitating the outlet) positioned to receive the impinging fluid flow after the impinging fluid flow impinges on the impingement layer and the impingement surface structures, to thereby provide an outlet fluid flow (e.g. ¶ 20, “Heated liquid and vapor produced from transfer of excess heat from the high power devices 115 to the liquid 210 is evacuated from the cooling chamber 215 and condensed through a heat exchanger 235 for storage into a tank 240 and recirculated to the jet head 220”). Re claim 2, 14 and 22-23, Bhunia teaches the jet impingement cooling assembly for semiconductor devices of claim 1, wherein the impingement surface structures form at least one impingement surface structure array (see 110 from left to right). Re claim 3 and 15, Bhunia teaches the jet impingement cooling assembly for semiconductor devices of claim 1, wherein a center of the at least one impingement surface structure array is linearly spaced from a center of the at least one jet nozzle (see Fig 2). Re claim 4 and 16, Bhunia teaches the jet impingement cooling assembly for semiconductor devices of claim 1, wherein the at least one impingement surface structure array includes an open zone in which no impingement surface structure is included, and a center of the open zone is aligned with a center of the at least one impingement surface structure array (see Fig 2). Re claim 7 and 18, Bhunia teaches the jet impingement cooling assembly for semiconductor devices of claim 1, wherein the at least one semiconductor device has a device area (area of 115 in Fig 2), and the impingement surface structures have a surface structure area that extends beyond the device area (see Fig 2). Re claim 8, Bhunia teaches the jet impingement cooling assembly for semiconductor devices of claim 1, wherein the surface structure area does not extend to a perimeter of the impingement layer (see Fig 2). Re claim 24, Bhunia teaches the method of claim 21, forming the impingement surface structures in alignment with at least one semiconductor device mounted on a mounting surface of the impingement layer that is opposed to the impingement surface, and aligned so that during disposing of the impingement layer within a heat exchange base causes the impingement surface to be disposed to receive an impinging fluid flow from at least one jet nozzle of a jet plate, to thereby provide jet impingement cooling of the at least one semiconductor device (see Fig 2). Allowable Subject Matter Claims 9-12, 17, 19-20, 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (see PTO-892). Any inquiry concerning this communication or earlier communications from the examiner should be directed to NELSON NIEVES whose telephone number is (571)270-0392. The examiner can normally be reached Monday to Friday 9am to 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Frantz Jules can be reached at 571-272-6681. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NELSON J NIEVES/Primary Examiner, Art Unit 3763 6/7/2026
Read full office action

Prosecution Timeline

Feb 06, 2024
Application Filed
Jun 10, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
92%
With Interview (+16.2%)
2y 6m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 803 resolved cases by this examiner. Grant probability derived from career allowance rate.

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