DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 7-9, filed December 15, 2025, with respect to the rejection(s) of claims 1 and 16 under U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. A new ground(s) of rejection is necessitated by the amendment. The deficiencies of Inamura in view of Liang are now met by Hiraishi. Applicant’s arguments with respect to claims 1and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8, 10-14 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inamura et al. US 4,806,857 A (hereinafter referred to as Name) in view of Liang et al. US 2013/0020694 A1 (hereinafter referred to as Liang) and further in view of Hiraishi JP 2004047838 A.
Regarding claim 1, Inamura discloses a testing apparatus (fig. 1, electrostatic breakdown voltage testing apparatus 201, col. 1, ln. 47-50) for, comprising: a first socket board (fig. 3, test table unit 231, col. 4, ln. 23-24) comprising a first withstand voltage test pin (fig. 1, 3, metal bar 204, col. 4, ln. 25-27); a second socket board (fig. 1, terminal base 205b, col. 3, ln. 19-20) comprising a second withstand voltage test pin (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45) and a direct current (DC) test pin (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45); a tester (fig. 1, tester 209, col. 3, ln. 35-36) configured to: generate a withstand voltage test signal (fig. 2, stp. B, col. 3, ln. 54-55), (fig. 1, drive unit 233, col. 4, ln. 25-28) transmit the withstand voltage test signal (fig. 2, stp. C-D, col. 3, ln. 56-68-col. 4, ln 1-2), to the first withstand voltage test pin and the second withstand voltage test pin generate a DC test signal (fig. 2, stp. B, col. 4, ln. 14-15), (fig. 1, drive unit 233, col. 4, ln. 25-28) and transmit the DC test signal (fig. 2, stp. C-E, col. 4, ln. 14-15) to the DC test pin; and a relay (fig. 1, relay 208, col. 3, ln. 34-37) configured to close and open an electrical connection between the tester and at least one of the first withstand planar voltage test pin (fig. 1, 3, metal bar 204, col. 4, ln. 25-27) the second withstand voltage test pin (fig. 1, one of terminal base 205a, col. 3, ln. 34-45), or the DC test pin.
Inamura does not disclose a power module; wherein the testing apparatus is configured to operate in the DC test mode or the withstand voltage test mode, and wherein the relay is configured to switch the testing apparatus between the DC test mode and the withstand voltage test mode by controlling (i) an electrical connection between the DC test pin and the tester and (ii) an electrical connection between the tester and each of the first and second withstand voltage test pins.
Liang discloses a power module (fig. 2, elm. 210, par. [0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide double sided cooled power module package having a single phase leg topology includes two IGBT and two diode semiconductor dies, the external die interconnections are through the bonded planar substrate material, power leads and signal leads, as taught in Liang in modifying the apparatus of Inamura. The motivation would be to reduce electrical parasitic inductance ,resistance and enhanced thermal management (see Liang: par. [0030]).
Hiraishi discloses wherein the testing apparatus (fig. 3, IV inspection system 11 and a withstand voltage tester 12, par. [0027]) is configured to operate in a DC test mode or a withstand voltage test mode (par. [0027], [0029], [0034], [0035]) and wherein the relay (fig. 3, 4, elm. 13, par. [0035]-[0036]) is configured to switch the testing apparatus (par. [0030]-[0035]) between the DC test mode (par. [0027], [0028]) and the withstand voltage test mode by controlling (i) an electrical connection between the DC test pin and the tester (fig. 3-4, elm. 11a, 11b, par. [0028]-[0031]) and (ii) an electrical connection between the tester and each of the first and second withstand voltage test pins (fig. 3-4, elm. 12a, 12b, par. [0028]-[0031]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an inspection apparatus for performing an IV inspection and an insulation test with an IV inspection device and a withstand voltage measuring device, as taught in Hiraishi in modifying the apparatus of Inamura and Liang. The motivation would be reduced inspection cost and time. (see Hiraishi: abs.).
Regarding claim 2, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 1, Inamura discloses wherein the first socket board (fig. 3, test table unit 231, col. 4, ln. 23-24) comprises (i) an upper socket board (fig. 3, bar drive base 234, col. 4, ln. 26-27) configured to face the upper substrate and (ii) a lower socket board (fig. 3, test table unit 231, col. 4, ln. 23-24) configured to face the lower substrate.
Inamura does not disclose wherein the power module comprises (i) a lower substrate (ii) an upper substrate disposed parallel to the lower substrate and (iii) a semiconductor device disposed between the lower substrate and the upper substrate.
Liang discloses wherein the power module (fig. 2, elm. 210, par. [0027]) comprises (i) a lower substrate (fig. 6, elm. 612, par. [0038]) (ii) an upper substrate (fig. 6, elm. 612, par. [0038]) disposed parallel to the lower substrate (see fig. 6), and (iii) a semiconductor device (fig. 6, elm. 610, par. [0038]) disposed between the lower substrate and the upper substrate.
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 3, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 2, Inamura discloses wherein the first withstand voltage test pin (fig. 1, 3, metal bar 204, col. 4, ln. 25-27) of the upper socket board (fig. 3, bar drive base 234, col. 4, ln. 26-27) is configured to contact at least a portion of the upper substrate (fig. 1, semiconductor element 5, Desc. 5th par.) (see fig. 1) and wherein the first withstand voltage test pin (fig. 1, metal plate 203, col. 2, ln. 49) of the lower socket board (fig. 3, test table unit 231, col. 4, ln. 23-24) is configured to contact at least a portion of the lower substrate (see fig. 1.).
Regarding claim 4, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 3, Inamura discloses wherein the second withstand voltage test pin (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45) and the DC test pin fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45) are configured to be in contact with the power lead and the signal lead, respectively.
Inamura does not disclose wherein the power module further comprises a power lead and a signal lead wherein at least a portion of each of the power lead and the signal lead is exposed to an outside of a housing of the power module.
Liang discloses wherein the power module (fig. 2, elm. 210, par. [0027]) further comprises a power lead (fig. 2, elm. 216, par. [0029]) and a signal lead (fig. 2, elm. 218, par. [0029]), wherein at least a portion of each of the power lead and the signal lead is exposed to an outside of a housing (fig. 2, elm. 200, par. [0027]) of the power module,
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 5, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 4, Liang discloses wherein the second socket board (fig. 1, terminal base 205b, col. 3, ln. 19-20) comprises (i) a power socket board (fig. 1, terminal base 205b on one side of 202, col. 3, ln. 19-20) configured to contact the power lead (fig. 1, power leads 202a, col. 2, ln. 54-56) and (ii) a signal socket board (fig. 1, terminal base 205b on the other side of 202, col. 3, ln. 19-20) configured to contact the signal lead (fig. 1, signal leads 202a, col. 2, ln. 54-56) wherein the power socket board and the signal socket board are disposed on sides of the lower socket board respectively (fig. 3, test table unit 231, col. 4, ln. 23-24).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 6, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 5, Liang discloses wherein the second withstand voltage test pin (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45) and the DC test pin (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45) of the power socket board (fig. 1, terminal base 205b on one side of 202, col. 3, ln. 19-20) are configured to contact at least a portion of the power lead (fig. 1, power leads 202a, col. 2, ln. 54-56), and wherein the second withstand voltage test pin and the DC test pin of the signal socket board (fig. 1, terminal base 205b on the other side of 202, col. 3, ln. 19-20) are configured to contact at least a portion of the signal lead (fig. 1, power leads 202a, col. 2, ln. 54-56).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 8, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 1, Inamura discloses wherein the second socket board (fig. 1, terminal base 205b, col. 3, ln. 19-20) further comprises a second plate (fig. 4b, elm. 232, col. 4, ln. 25), wherein the DC test pin (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45) is one of a plurality of DC test pins (see fig. 1) that are located at the second plate and configured to face the power module (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45), and wherein the second withstand voltage test pin (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45) is located between the plurality of DC test pins (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45) and configured to face the power module (see fig. 1).
Regarding claim 10, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 9, Inamura discloses wherein the relay (fig. 1, relay 208, col. 3, ln. 34-37) is configured to, in the DC test mode (fig. 2, stp. C-E, col. 4, ln. 14-15), electrically connect the tester (fig. 1, tester 209, col. 3, ln. 35-36) to the DC test pin (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45).
Regarding claim 11, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 9, Inamura discloses wherein the relay (fig. 1, relay 208, col. 3, ln. 34-37) is configured to, in the withstand voltage test mode, electrically connect the tester(fig. 1, tester 209, col. 3, ln. 35-36) to the first withstand voltage test pin (fig. 1, 3, metal bar 204, col. 4, ln. 25-27) and the second withstand voltage test pin (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45).
Regarding claim 12, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 9, Inamura discloses, wherein the relay is one of a plurality of relays (see fig. 1, relay 208, col. 3, ln. 34-37) that are connected (ii) between the second withstand voltage test pin (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45) and the tester (fig. 1, tester 209, col. 3, ln. 35-36),, and (iii) between the DC test pin (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45) and the tester.
Inamura, Liang and Hiraishi do not disclose relay connected (i) between the first withstand voltage test pin and the tester. However the relay connected between the first withstand voltage test pin and the tester absent any criticality, is only considered to be an obvious choice of for providing a switch (relay) between two devices. Since it appears to the Examiner that the choice of a relay is nothing more than one of numerous types of switches that a person having ordinary skill in the art will find obvious to provide. In this case to provide to connect or disconnect two devices.
Regarding claim 13, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 12, Inamura discloses wherein the plurality of relays (see fig. 1, relay 208, col. 3, ln. 34-37) comprise: a first relay configured to be closed and connected to the DC test pin (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45) in the DC test mode (fig. 2, stp. C-E, col. 4, ln. 14-15), and a second relay configured to be open and connected to the first withstand voltage test pin (fig. 1, 3, metal bar 204, col. 4, ln. 25-27), and the second withstand voltage test pin (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45) in the DC test mode.
Regarding claim 14, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 12, Inamura discloses wherein the plurality of relays (see fig. 1, relay 208, col. 3, ln. 34-37) comprise: a first relay (see fig. 1) configured to be closed and connected to the first withstand voltage test pin (fig. 1, 3, metal bar 204, col. 4, ln. 25-27) and the second withstand voltage test pin (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45) in the withstand voltage test mode; and a second relay (see fig. 1) configured to be open and connected to the DC test pin (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45) in the withstand voltage test mode (fig. 2, stp. C-D, col. 3, ln. 56-68-col. 4, ln 1-2).
Regarding claim 16, Inamura discloses a method of testing a power module (fig. 1, IC 202, col. 2, ln 56), comprising: mounting the power module on a testing apparatus (fig. 1, electrostatic breakdown voltage testing apparatus 201, col. 1, ln. 47-50); performing a direct current (DC) test (fig. 2, stp. C-E, col. 4, ln. 14-15) of the power module by operating the testing apparatus in a DC test mode (fig. 2, stp. C-E, col. 4, ln. 14-15); and perform a withstand voltage test (fig. 2, stp. C-D, col. 3, ln. 56-68-col. 4, ln 1-2), of the power module by operating the testing apparatus in a withstand voltage test mode (fig. 2, stp. C-D, col. 3, ln. 56-68-col. 4, ln 1-2), wherein the testing apparatus comprises: a first socket board (fig. 3, test table unit 231, col. 4, ln. 23-24) comprising a first withstand voltage test pin (fig. 1, 3, metal bar 204, col. 4, ln. 25-27), a second socket board (fig. 1, terminal base 205b, col. 3, ln. 19-20) comprising a second withstand voltage test pin (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45), and a DC test pin (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45) a tester (fig. 1, tester 209, col. 3, ln. 35-36) configured to generate a withstand voltage test signal and a DC test signal, and a relay (fig. 1, relay 208, col. 3, ln. 34-37) configured to switch an operating mode of the testing apparatus to the DC test mode (fig. 2, stp. C-E, col. 4, ln. 14-15) or the withstand voltage test mode (fig. 2, stp. C-D, col. 3, ln. 56-68-col. 4, ln 1-2), and wherein mounting the power module on the testing apparatus comprises contacting the power module with the first withstand voltage test pin, the second withstand voltage test pin, and the DC test pin (see, fig. 1).
Inamura does not disclose for a power module; wherein the testing apparatus is configured to operate in the DC test mode or the withstand voltage test mode, and wherein the relay is configured to switch the testing apparatus between the DC test mode and the withstand voltage test mode by controlling (i) an electrical connection between the DC test pin and the tester and (ii) an electrical connection between the tester and each of the first and second withstand voltage test pins.
Liang discloses for a power module (fig. 2, elm. 210, par. [0027]).
The references are combined for the same reason already applied in the rejection of claim 1.
Hiraishi discloses wherein the testing apparatus (fig. 3, IV inspection system 11 and a withstand voltage tester 12, par. [0027]) is configured to operate in a DC test mode or a withstand voltage test mode (par. [0027], [0029]) and wherein the relay (fig. 3, 4, elm. 13, par. [0035]-[0036]) is configured to switch the testing apparatus (par. [0030]-[0035]) between the DC test mode (par. [0027], [0028]) and the withstand voltage test mode by controlling (i) an electrical connection between the DC test pin and the tester (fig. 3-4, elm. 11a, 11b, par. [0028]-[0031]) and (ii) an electrical connection between the tester and each of the first and second withstand voltage test pins (fig. 3-4, elm. 12a, 12b, par. [0028]-[0031]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 17, Inamura, Liang and Hiraishi discloses the method of claim 16, Inamura discloses wherein performing the DC test (fig. 2, stp. C-E, col. 4, ln. 14-15) of the power module comprises electrically connecting, by the relay (fig. 1, relay 208, col. 3, ln. 34-37), the tester (fig. 1, tester 209, col. 3, ln. 35-36) to the DC test pin (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45).
Regarding claim 18, Inamura, Liang and Hiraishi discloses the method of claim 16, Inamura discloses wherein performing the withstand voltage test (fig. 2, stp. C-D, col. 3, ln. 56-68-col. 4, ln 1-2), of the power module comprises electrically connecting, by the relay (fig. 1, relay 208, col. 3, ln. 34-37), the tester (fig. 1, tester 209, col. 3, ln. 35-36) to the first withstand voltage test pin (fig. 1, 3, metal bar 204, col. 4, ln. 25-27) and the second withstand voltage test pin (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45).
Regarding claim 19, Inamura, Liang and Hiraishi discloses the method of claim 16, Inamura discloses wherein the relay comprises a plurality of relays (see fig. 1, relay 208, col. 3, ln. 34-37) (i) Inamura and Liang do not discloses connected between the first withstand voltage test pin and the tester, (ii) between the second withstand voltage test pin (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45) and the tester (fig. 1, tester 209, col. 3, ln. 35-36), and (iii) between the DC test pin (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45) and the tester.
Inamura, Liang and Hiraishi do not disclose relay connected between the first withstand voltage test pin and the tester. However the relay connected between the first withstand voltage test pin and the tester absent any criticality, is only considered to be an obvious choice of for providing a switch (relay) between two devices. Since it appears to the Examiner that the choice of a relay is nothing more than one of numerous types of switches that a person having ordinary skill in the art will find obvious to provide. In this case to provide to connect or disconnect two devices.
Regarding claim 20, Inamura, Liang and Hiraishi discloses the method of claim 19, Inamura discloses wherein the plurality of relays (see fig. 1, relay 208, col. 3, ln. 34-37) comprise: a first relay (see fig. 1) configured to be closed and connected to the DC test pin (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45) in the DC test mode (fig. 2, stp. C-E, col. 4, ln. 14-15); and a fourth relay configured to be open and connected to the DC test pin (fig. 1, separate one of terminal base 205a, col. 3, ln. 19-20, 34-45) in the withstand voltage test mode (fig. 1, one of terminal base 205a, col. 3, ln. 19-20, 34-45).
Inamura, Liang and Hiraishi do not disclose a second relay configured to be open and connected to the first withstand voltage test pin and the second withstand voltage test pin in the DC test mode; a third relay configured to be closed and connected to the first withstand voltage test pin and the second withstand voltage test pin in the withstand voltage test. However the second relay configured to be open and connected to the first withstand voltage test pin and the second withstand voltage test pin in the DC test mode; a third relay configured to be closed and connected to the first withstand voltage test pin and the second withstand voltage test pin in the withstand voltage test absent any criticality, is only considered to be an obvious choice of for providing a switches (relays) between two devices. Since it appears to the Examiner that the choice of a relay is nothing more than one of numerous types of switches that a person having ordinary skill in the art will find obvious to provide. In this case to provide to connect or disconnect two devices.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inamura in view of Liang in view of Hiraishi as applied to claim 1 above, and further in view of Isofuku et al. JP 2000206177 A (hereinafter referred to as Isofuku).
Regarding claim 7, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 1, Inamura discloses wherein the first socket board (fig. 3, test table unit 231, col. 4, ln. 23-24) further comprises a first plate (fig. 1, metal plate 203, col. 2, ln. 49).
Inamura, Liang and Hiraishi do not disclose the wherein the first withstand voltage test pin is located at the first plate and configured to face the power module.
Isofuku disclose the wherein the first withstand voltage test pin (fig. 14, center conductor 131 of the coaxial cable 130, par. [0026]) is located at the first plate (fig. 14, elm. 130, par. [0026]) and configured to face the power module (fig. 14, elm. 200, par. [0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an electrostatic breakdown test for semiconductor devices, as taught in Isofuku in modifying the apparatus of Inamura, Liang and Hiraishi. The motivation would be to which enhance the reliability on measurement of a breakdown endurance amount by static discharging of the semiconductor device (see Isofuku: abs).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inamura in view of Liang in view of Hiraishi as applied to claim 1 above, and further in view of Feng et al. CN 109449051 A (hereinafter referred to as Feng).
Regarding claim 15, Inamura, Liang and Hiraishi discloses the testing apparatus of claim 12, Inamura, Liang and Hiraishi do not disclose wherein the plurality of relays comprise a cylinder relay.
Feng discloses wherein the plurality of relays comprise a cylinder relay (fig. 1, clm. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a cylinder-type multi-contact relay, as taught in Feng in modifying the apparatus of Inamura, Liang and Hiraishi. The motivation would be the spring can pull the rotating rod back to achieve automatic reset after the moving contact and the static contact are powered off. (see Feng: The invention has the following advantages).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
LIN et al CN 216870764 U discloses a detection device of a DC/DC module. The detection device comprises a controller, a programmable power supply, an insulation and voltage resistance tester, a voltage electronic load tester, a multi-channel oscilloscope, a bottom plate and a plurality of detection modules arranged on the bottom plate. Each detection module comprises a first switching assembly, a second switching assembly and a third switching assembly, through the first switching assembly, the second switching assembly and the third switching assembly, the input end of the DC/DC module to be tested can be connected with the output end of the programmable power supply, and the output end of the DC/DC module to be tested can be connected with a voltage electronic load tester or a multi-channel oscilloscope. Or, the input end of the to-be-tested DC/DC module is in short circuit, the output end of the to-be-tested DC/DC module is in short circuit, and meanwhile the input end and the output end of the to-be-tested DC/DC module are connected with the insulation and voltage resistance tester. Based on the detection device disclosed by the invention, the possibility of errors of the detection result can be reduced, and the detection efficiency is improved.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY G MCDONNOUGH whose telephone number is (571)272-6552. The examiner can normally be reached M-F 8 am-5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EMAN ALKAFAWI can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY G MCDONNOUGH/Examiner, Art Unit 2858
/NASIMA MONSUR/Primary Examiner, Art Unit 2858