DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on July 14, 2026, is acknowledged. Claims 16-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Accordingly, claims 1-15 are ready for examination.
Drawings
The drawings are objected to because first extension height 1301-HE appears to be pointing to the wrong element in Fig. 14. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 11-15 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 11, the claim recites the limitation "the first nanostack" in line 3 and “the second nanostack” in line 4. There is insufficient antecedent basis for these limitations in the claim. For purpose of compact prosecution, “the first nanostack” and “the second nanostack” will be treated as if they were “a first nanostack” and “a second nanostack”. Claims 12-14 which either directly or indirectly depend from claim 11 and which inherit issues of claim 11, are rejected for similar reasons.
With respect to claim 15, the claim recites “the first extension region height” in lines 24-25. There is insufficient antecedent basis for this limitation in the claim. Moreover, the claim recites “a middle dielectric isolation width” in lines 28-29 and “a width of the middle dielectric isolation layer” in lines 30-31. It is not clear if the middle dielectric isolation width and the width of the middle dielectric isolation layer are referring to the same dimension of the middle dielectric isolation layer or different dimensions. For purpose of compact prosecution, “the first extension region height” will be treated as if it were “a third dielectric layer” and it will be assumed that that the middle dielectric isolation width and the width of the middle dielectric isolation layer are referring to the same dimension of the middle dielectric isolation layer.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jo et al. (US 2023/0352529, hereinafter “Jo”).
Regarding claim 1, Jo teaches in Fig. 1A-1C (shown below) and related text a semiconductor structure comprising:
a substrate (105, Fig. 1C and ¶[0031]);
a first channel stack (110, Fig. 1C and ¶[0032]) on the substrate (105, Fig. 1C) having one or more first channel layers (110C, Fig. 1C and ¶[0032]) and having a first width (Fig. 1C);
a second channel stack (120, Fig. 1C and ¶[0032]) having one or more channel layers (120C, Fig. 1A and ¶[0036]) and having a second width (Fig. 1C) wherein the second channel stack is vertically aligned above the first channel stack (Fig. 1C); and
wherein the first width is greater than the second width (Fig. 1C).
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Regarding claim 2 (1), Jo teaches wherein the first channel stack is part of a p-type field effect transistor (¶[0038]) and the second channel stack is part of an n-type field effect transistor (¶[0038]).
Regarding claim 3 (1), Jo further teaches:
a middle dielectric isolation layer (130, Fig. 1C and ¶[0033]) separating the first channel stack (110, Fig. 1C) and the second channel stack (120, Fig. 1C).
Regarding claim 4 (3), Jo further teaches wherein the middle dielectric isolation layer has a width (Fig. 1C), and wherein the second width (i.e. width of 120C, Fig. 1C) is less than the width of the middle dielectric isolation layer (i.e. width of 130, Fig. 1C).
Regarding claim 5 (4), Jo discloses wherein the first width (i.e. width of 110C, Fig. 1C) is the same as the width of the middle dielectric isolation layer (i.e. width of 130, Fig. 1C).
Regarding claim 6 (1), Jo further teaches a lower dielectric isolation layer (115D, Fig. 1C and ¶[0044]) separating the first channel stack (110, Fig. 1C) and the substrate (105, Fig. 1C).
Regarding claim 7 (6), Jo teaches wherein the lower dielectric isolation layer has a width, and wherein the second width (i.e. width of 120C, Fig. 1C) is less than the width of the lower dielectric isolation layer (115D, Fig. 1C).
Regarding claim 8 (7), Jo teaches wherein the first width (i.e. width of 110C, Fig. 1C) is the same as a width of a middle dielectric isolation layer (i.e. width of 130, Fig. 1C) separating the first channel stack (110, Fig. 1C) and the second channel stack (120, Fig. 1C).
Claim(s) 1-2 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2023/0352528, hereinafter “Park `528”).
Regarding claim 1, Park `528 teaches in Figs. 3, 13A-13B (shown below) and related text a semiconductor structure comprising:
a substrate (305, Fig. 3 and ¶[0057]);
a first channel stack (30L, Fig. 3 and ¶[0058]) on the substrate (305, Fig. 3) having one or more first channel layers (310c, Fig. 3 and ¶[0058]) and having a first width (Fig. 3);
a second channel stack (30U, Fig. 3 and ¶[0057]) having one or more channel layers (320C, Fig. 3 and ¶[0057]) and having a second width (Fig. 3) wherein the second channel stack is vertically aligned above the first channel stack; and
wherein the first width is greater than the second width (Fig. 3).
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Regarding claim 2 (1), Park `528 teaches wherein the first channel stack is part of a p-type field effect transistor (¶[0115]) and the second channel stack is part of an n-type field effect transistor (¶[0115]).
Regarding claim 9 (1), Park `528 further teaches
at least one first inner spacer (165, Fig. 13A) having a first thickness (Figs. 3 and Fig. 13A) separating adjacent first channel layers (310C, 210C, Figs. 3 and 13A); and
at least one second inner spacer (165, Fig. 13A) having a second thickness (Figs. 3 and 13A) separating adjacent second channel layers (320C, 220C, Figs. 3 and 13A);
wherein the first thickness is greater than the second thickness (i.e. when the structure in Fig. 13A is built to surround the structure in Fig. 3 rather than the structure in Fig. 2, the first thickness of the first inner spacer could be greater than the second thickness of the second inner spacer, ¶[0115]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2025/0254989, hereinafter “Park `989”) in view of Park et al. (US 2023/0352528, hereinafter Park `528).
Regarding claim 1, Park `989 teaches in Figs. 2A and 3B (shown below) and related text a semiconductor structure comprising:
a substrate (101, Fig. 3 and ¶[0056]);
a first channel stack (Ch1, Fig. 3B and ¶[0056]) on the substrate (101, Figs. 2A and 3B) having one or more first channel layers (110, Figs. 2A, 3B and ¶[0057]) and having a first width (Fig. 3B); and
a second channel stack (CH2, Figs. 2A, 3B and ¶[0057]) having one or more channel layers (220, Figs. 2A, 3B and ¶[0053]) and having a second width (Fig. 3B) wherein the second channel stack is vertically aligned above the first channel stack (Fig. 3B).
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While Park `989 teaches in the non-provisional application that the first width of the first channel is greater than the second width of the second channel (Fig. 3B), Park `989 does not explicitly teach that the first width is greater than the second width in the provisional application. Nonetheless, forming the first channel and the second channel disclosed by Park `989, so that the width of the first channel is greater than the width of the second channel would be obvious to one of ordinary skill in the art as evidenced by Park `528. Specifically, Park `528, in a similar field of endeavor, teaches that when forming a CFET, similar to that disclosed by Park `989, the first channel width (W1, Fig. 1A) can be greater than the second channel width (W2, Fig. 1) in order to facilitate connection to source/drain regions of the lower transistor (¶[0040]).
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first channel with the width greater than the width of the second channel in order to facilitate connection to source/drain regions of the lower transistor.
Regarding claim 9 (1), the combined teaching of Park `989 and Park `528 was further discloses at least one first inner spacer (103, Fig. 2A) having a first thickness (Fig. 2A) separating adjacent first channel layers (110, Fig. 2A), and at least one second inner spacer (203, Fig. 2A) having a second thickness (Fig. 2A and ¶¶[0051]) separating adjacent second channel layers (220, Fig. 2A). While Park `989 and Park `528, do not explicitly teach in the embodiment shown in Fig. 2A of Park `989 that the first thickness is greater than the second thickness, Park `989 and Park `528, nonetheless teach that positions of the n-type (T1’ transistor) and p-type (T2’ transistor) transistors can be reversed in order to meet specific design requirements (Park `989, ¶[0035] and Park `528, ¶[0045]), which would lead to the first thickness of the first inner spacer being greater than the thickness of the second inner spacer.
Accordingly, it would have been obvious to one of ordinary skill in the art to change the position of T1` and T2’ transistor disclosed by Park `989 and Park `528, so that T2’ becomes a lower transistor and T1’ becomes an upper transistor, and, as a result, the first inner spacer having a thickness that is greater of a thickness of the second inner spacer, in order to meet specific design requirements.
Regarding claim 10 (9), the combined teaching of Park `989 and Park `528 discloses wherein:
the one or more first channel layers (i.e. in modified Park `898, 220, Fig. 2A) has a first extension height between the at least one first inner spacers (i.e. in modified Park `989, extension height between spacers 203, Fig. 2A);
the one or more second channel layers (i.e. in modified Park `898, 110, Fig. 2A) has a second extension height between the at least one second inner spacers (i.e. in modified Park `989, extension height between spacers 103, Fig. 2A); and
the second extension height is greater than the first extension height (modified Park `989, Fig. 2A).
Regarding claim 11 (10), the combined teaching of Park `989 and Park `528 was discussed above in the rejection of claim 10 and further includes a gate material (Park `989, 150A, 250A and ¶¶[0042] and [0049]), around the one or more first channel layers (Park `989, 220, Fig. 2A) and the one or more second channel layers (Park `989, 110, Fig. 2A), wherein the gate material has a first suspension thickness in a first nanostack (Park `989, i.e. gate thickness between adjacent first channels 220, Fig. 2A), the gate material has a second suspension thickness in the second nanostack (Park `989, i.e. gate thickness between adjacent first channels 110, Fig. 2A) and the second suspension thickness is the same as the first suspension thickness (Park `989).
Relevant Prior Art
Ther prior art of record and not relied upon is considered pertinent to Applicant’s disclosure:
Frougier et al. (US 2024/0186391) teaches first gate suspension thickness and second gate suspension thickness being the same.
Mannebach et al. (US 2025/0220959) teaches that channel layers can be made of different materials including silicon body cladded with silicon germanium.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM.
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/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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