Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to the restriction sent out on 03/26/2026, applicant elects, per correspondence on 04/22/2026, invention I claims 1-7 and 16-20 to be examined upon the merits below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-7, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 20220208757) in view of Yu et al (US 20220392797).
Regarding claims 1 and 16, Do et al teaches
[claim 1] A semiconductor structure comprising: a deep trench via in a diffusion region (figure 8, paragraph 0092, where element TVI is the deep trench via [elements 162 and 164] in a diffusion region [region situated between both S/D regions]);
a frontside metal wire conductively connected to a top surface of the deep trench via (figure 8, paragraph 0080 and 0084, element M2L is the frontside [top side] metal wire electrically connected to the deep trench via [element TVI] through elements VDD [M1L] and element V2A/B),
and a backside metal wire conductively connected to a bottom surface of the deep trench via (figure 8, paragraph 0086, where element PWL2 is the backside metal wire conductively connected to the bottom surface of the deep trench via [through elements PWI, PWV and PWL1]),
wherein the frontside metal wire and the backside metal wire are parallel to each other and orthogonal to the deep trench via (figure 8, paragraphs 0080 and 0086, where elements M2L and PWL2 are both orthogonal [extend in the horizontal direction] to the deep trench via [TVI, which extends in a vertical direction] and both the frontside and backside metal wires are parallel to each other [they both extend in the horizontal direction]).
[claim 16] A semiconductor structure comprising: a deep trench via in a diffusion region (figure 8, paragraph 0092, where element TVI is the deep trench via [elements 162 and 164] in a diffusion region [region situated between both S/D regions]);
a frontside metal wire conductively connected to a top surface of the deep trench via through a frontside via (figure 8, paragraph 0080 and 0084, element M2L is the frontside [top side] metal wire electrically connected to the deep trench via [element TVI] through elements VDD [M1L] and element V2A/B which comprise the frontside via);
and a backside metal wire conductively connected to a bottom surface of the deep trench via through a backside via and a backside contact (figure 8, paragraph 0086, where element PWL2 is the backside metal wire conductively connected to the bottom surface of the deep trench via [through elements PWI, PWV and PWL1 which comprise the backside via and backside contact]),
wherein the frontside metal wire and the backside metal wire are not vertically aligned but parallel to each other (figure 8, paragraphs 0080 and 0086, where element M2L and PWL2 are not vertically aligned, they do overlap but their alignment is not precisely the same, yet they are both parallel to each other [horizontal direction]),
and a first direction of the frontside metal wire and a second direction of the backside metal wire are orthogonal to a length direction of the deep trench via (figure 8, paragraphs 0080 and 0086, where elements M2L and PWL2 are extending in the horizontal direction which is orthogonal to the vertical direction which is the length direction of the deep trench via [element TVI]).
However, Do et al does not specifically disclose
[claim 1] double [diffusion region]
[claim 16] double [diffusion region] between a first dummy metal gate and a second dummy metal gate;
However, Yu et al does teach
[claim 1] double [diffusion region] (figure 2, paragraph 0019, where element 210 is in the location of the deep trench via from Do et al, and is located in a double diffusion region as labeled under Double Diffusion Break Area [DDB]).
[claim 16] double [diffusion region] between a first dummy metal gate and a second dummy metal gate (figure 2, paragraph 0019, 0020 and 0030, where element 210 is in the location of the deep trench via from Do et al, and is located in a double diffusion region as labeled under Double Diffusion Break Area [DDB] and situated between two dummy gates, elements 213 which are initially formed as dummy gates and then replaced as normal gates).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Do et al to incorporate the teachings of Yu et al in order use a double diffusion region for specific use cases to optimize performance of the device, such as reducing breakdown voltage at higher frequencies and optimizing current amplification.
Regarding claims 6, 7 and 20,
DO et al further discloses
[claim 6] The semiconductor structure of claim 1, further comprising a frontside via, a backside via, and a backside contact (figure 8, paragraphs 0080 and 0086, where element V2B/A ist he front side via, element PWL1 is the backside contact and element PWI is the backside via),
wherein the frontside metal wire is conductively connected to the top surface of the deep trench via through the frontside via (figure 8, paragraph 0084, where element VDD is connected to the topside metal wire [element M2L] and is connected to the top of the deep trench via [element TVI]),
and the backside metal wire is conductively connected to the bottom surface of the deep trench via through the backside via and the backside contact (figure 8, paragraphs 0080 and 0086, where element PWL1 is the backside contact and is connected to the backside metal wire [element PWL2] through element PWI).
[claim 7] The semiconductor structure of claim 1, wherein the frontside metal wire is not vertically aligned with the backside metal wire and a horizontal distance between the frontside and backside metal wires is less than a length of the deep trench via (figure 8, paragraphs 0080 and 0086, where elements PWL2 and M2L are the backside and frontside metal wire’s and they are not vertically aligned [they do not have the same dimensions in the horizontal direction and thus are not vertically aligned], and the separation of the two in the horizontal direction is minimal [as there is overlap] and thus the distance between the two in the horizontal direction is substantially less than the length of the deep trench via [TVI] in the vertical direction).
[claim 20] The semiconductor structure of claim 16, wherein a horizontal distance between the frontside metal wire and the backside metal wire is less than the length of the deep trench via (figure 8, paragraphs 0080 and 0086, where elements PWL2 and M2L are the backside and frontside metal wire’s and the separation of the two in the horizontal direction is minimal [as there is overlap] and thus the distance between the two in the horizontal direction is substantially less than the length of the deep trench via [TVI] in the vertical direction).
Regarding claims 2-4, and 17-19
Do et al as modified above teaches all of the limitations of the parent claim, claim 1 and 16, but does not specifically disclose
[claim 2] The semiconductor structure of claim 1, further comprising a first dummy metal gate and a second dummy metal gate, wherein the double diffusion region is between the first dummy metal gate and the second dummy metal gate and the top surface of the deep trench via is at or above a top surface of the first dummy metal gate and the second dummy metal gate.
[claim 3] The semiconductor structure of claim 2, further comprising a first set of nanosheets surrounded by the first dummy metal gate and a first set of inner spacers next to the first set of nanosheets, and a second set of nanosheets surrounded by the second dummy metal gate and a second set of inner spacers next to the second set of nanosheets, wherein the deep trench via is between the first set of inner spacers and the second set of inner spacers.
[claim 4] The semiconductor structure of claim 3, further comprising a first sidewall spacer at a sidewall of the first dummy metal gate and a second sidewall spacer at a sidewall of the second dummy metal gate, wherein the deep trench via is insulated from the first and the second dummy metal gate by the first and the second sidewall spacer and from the first and the second set of nanosheets by the first and the second set of inner spacers.
[claim 17] The semiconductor structure of claim 16, wherein the top surface of the deep trench via is at or above a top surface of the first dummy metal gate and the second dummy metal gate.
[claim 18] The semiconductor structure of claim 17, further comprising a first set of nanosheets surrounded by the first dummy metal gate and a first set of inner spacers next to the first set of nanosheets, and a second set of nanosheets surrounded by the second dummy metal gate and a second set of inner spacers next to the second set of nanosheets, wherein the deep trench via is between the first set of inner spacers and the second set of inner spacers.
[claim 19] The semiconductor structure of claim 18, further comprising a first sidewall spacer at a sidewall of the first dummy metal gate and a second sidewall spacer at a sidewall of the second dummy metal gate, wherein the deep trench via is insulated from the first and the second dummy metal gate by the first and the second sidewall spacer and insulated from the first and the second set of nanosheets by the first and the second set of inner spacers.
However, Yu et al does teach
[claim 2] The semiconductor structure of claim 1, further comprising a first dummy metal gate and a second dummy metal gate, wherein the double diffusion region is between the first dummy metal gate and the second dummy metal gate and the top surface of the deep trench via is at or above a top surface of the first dummy metal gate and the second dummy metal gate (figure 2, paragraph 0020, where elements 213 [before gates are formed are the dummy gates] are at the same height as the deep trench via [read into from Do et al] which is element 210).
[claim 3] The semiconductor structure of claim 2, further comprising a first set of nanosheets surrounded by the first dummy metal gate and a first set of inner spacers next to the first set of nanosheets, and a second set of nanosheets surrounded by the second dummy metal gate and a second set of inner spacers next to the second set of nanosheets (figure 2, paragraphs 0020, and 0029, where the finFET device shown can comprise nanosheets [element 205] surrounded by two [first and second] dummy gates [elements 213 before they’re formed into real gates as noted in paragraph 0029], each gate with a set of inner spaces [element 216 next to element 215] next to the nanosheets [elements 205], where the first set of nanosheets, dummy gate and inner spacer is on the left-hand side of element 210 [the deep trench via as read into from Do et al], where the second set of nanosheets, dummy gate and inner spacer is on the right-hand side of element 210),
wherein the deep trench via is between the first set of inner spacers and the second set of inner spacers (figure 2, paragraphs 0020 and 0029, where element 210 is the deep trench via read into from Do et al and is situated between the first and second inner spaces [elements 216 on either side of element 210]).
[claim 4] The semiconductor structure of claim 3, further comprising a first sidewall spacer at a sidewall of the first dummy metal gate and a second sidewall spacer at a sidewall of the second dummy metal gate (figure 2, paragraph 0020, where element 216 immediately on the left-hand side of element 210 [on the right-hand side of element 213 on the left-hand side of element 210] is the first sidewall spacer at the first dummy gate [element 213 on the left-hand side of element 210], where element 216 immediately on the right-hand side of element 210 is the second sidewall spacer on a sidewall of the second dummy metal gate [element 213 on the right-hand side of element 210]),
wherein the deep trench via is insulated from the first and the second dummy metal gate by the first and the second sidewall spacer and from the first and the second set of nanosheets by the first and the second set of inner spacers (figure 2, paragraph 0020, where the deep trench via [element 210 as read into from Do et al] is isolated from the first and second dummy gate [elements 213 on the left-hand side and right-hand side respectively] as well as the nanosheets [element 205] on either side of the deep trench via [element 210 as read into from Do et al]).
[claim 17] The semiconductor structure of claim 16, wherein the top surface of the deep trench via is at or above a top surface of the first dummy metal gate and the second dummy metal gate (figure 2, paragraph 0020, where elements 213 [before gates are formed are the dummy gates] are at the same height as the deep trench via [read into from Do et al] which is element 210).
[claim 18] The semiconductor structure of claim 17, further comprising a first set of nanosheets surrounded by the first dummy metal gate and a first set of inner spacers next to the first set of nanosheets, and a second set of nanosheets surrounded by the second dummy metal gate and a second set of inner spacers next to the second set of nanosheets (figure 2, paragraphs 0020, and 0029, where the finFET device shown can comprise nanosheets [element 205] surrounded by two [first and second] dummy gates [elements 213 before they’re formed into real gates as noted in paragraph 0029], each gate with a set of inner spaces [element 216 next to element 215] next to the nanosheets [elements 205], where the first set of nanosheets, dummy gate and inner spacer is on the left-hand side of element 210 [the deep trench via as read into from Do et al], where the second set of nanosheets, dummy gate and inner spacer is on the right-hand side of element 210),
wherein the deep trench via is between the first set of inner spacers and the second set of inner spacers (figure 2, paragraphs 0020 and 0029, where element 210 is the deep trench via read into from Do et al and is situated between the first and second inner spaces [elements 216 on either side of element 210]).
[claim 19] The semiconductor structure of claim 18, further comprising a first sidewall spacer at a sidewall of the first dummy metal gate and a second sidewall spacer at a sidewall of the second dummy metal gate (figure 2, paragraph 0020, where element 216 immediately on the left-hand side of element 210 [on the right-hand side of element 213 on the left-hand side of element 210] is the first sidewall spacer at the first dummy gate [element 213 on the left-hand side of element 210], where element 216 immediately on the right-hand side of element 210 is the second sidewall spacer on a sidewall of the second dummy metal gate [element 213 on the right-hand side of element 210]),
wherein the deep trench via is insulated from the first and the second dummy metal gate by the first and the second sidewall spacer and insulated from the first and the second set of nanosheets by the first and the second set of inner spacers (figure 2, paragraph 0020, where the deep trench via [element 210 as read into from Do et al] is isolated from the first and second dummy gate [elements 213 on the left-hand side and right-hand side respectively] as well as the nanosheets [element 205] on either side of the deep trench via [element 210 as read into from Do et al]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Do et al to incorporate the teachings of Yu et al in order use to place the deep trench via between dummy gates with a certain heigh in a double diffusion region for specific use cases to optimize performance of the device, such as reducing breakdown voltage at higher frequencies and optimizing current amplification.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 20220208757), and Yu et al (US 20220392797) and in further view of Yemenicioglu et al (US 20230420512).
Do et al as modified teaches all of the limitations of the parent claim 2, but does not specifically disclose
[claim 5] The semiconductor structure of claim 2, further comprising a first nanosheet transistor having a first source/drain (S/D) region adjacent to the first dummy metal gate, a second nanosheet transistor having a second S/D region adjacent to the second dummy metal gate, a backside contact contacting the deep trench via from underneath thereof, and a backside S/D contact contacting the first S/D region from underneath thereof, wherein a height of the backside contact is lower than a height of the backside S/D contact.
However Yemenicioglu et al does teach
[claim 5] The semiconductor structure of claim 2, further comprising a first nanosheet transistor having a first source/drain (S/D) region adjacent to the first dummy metal gate (figures 3 and 4A, and paragraphs 0051 and 0089, where elements 424 are the nanosheets associated with element 304A of figure 3 which is adjacent to a dummy gate, element 302, which eventually is replaced with metal gate lines but per paragraph 0089 they are established first as dummy gates, where the first set of nanosheet transistors is element 424 on the right-hand side of the deep trench via [element TCN DV]),
a second nanosheet transistor having a second S/D region adjacent to the second dummy metal gate (figures 3 and 4A, paragraphs 0051 and 0089, where the left-hand side of element TCN DV [deep trench via] of figure 4A is also adjacent to the dummy gate [element 304A of figure 3]),
a backside contact contacting the deep trench via from underneath thereof (figure 4A, paragraph 0059, where element MO is the backside contact which contacts the deep trench via [element TCN DV] from the backside [above] – note Bo et al as modified has the backside being underneath, but if one flips the devices upside down, which causes no change in functionality, the backside of Do et al as modified is on top of the structure as shown in figure 4A in Yemenicioglu),
and a backside S/D contact contacting the first S/D region from underneath thereof, wherein a height of the backside contact is lower than a height of the backside S/D contact (figure 3, paragraph 0051, where element 308 is the contact of the source/drain situated on a backside [top of structure as shown in figure 3, but if rotated 180 degrees it is designated as ‘underneath’] where the height of element 308 is below element M0 [as shown in figure 3 by M0 being placed over element 308]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Do et al to incorporate the teachings of Yemenicioglu et al in order use to place the deep trench between source drain contacts with connections at different layers than the source/drain contacts in order to first form a functioning transistor with source/drain while keeping connection with deep trench via to maximize spatial efficiency by using a contact between the source/drain while also keeping a functioning transistor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Reznicek et al (US 20210288046), Otsubo et al (US 20200403072), Wang et al (US 20190378836), Chen et al (US 20170287933), Xie et al (US 9362181), Zhu (US 20100224876), Kunnen (US 20060131655) as devices with deep trench situated between transistors.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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