DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 11, 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8, 14-16, and 21-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claims 6 and 7, the limitation “pixel oxide islands” is never defined in claim 1. Thus, the limitation renders the claims indefinite and clarification is required. As to claim 8, the “depth G” is defined by two oxide arrays 236 and 240 as seen in FIG. 4 of the Drawings. Since claim 1 only defines one oxide array 236, it does not appears “the depth G is between about 1µm and about 3µm” as recited. It is not clear whether “about” encompasses a broader interpretation of the disclosure. Thus, the limitation renders the claim indefinite and clarification is required. As to claims 14 and 15, the limitation “logic oxide islands” is never defined in claim 9. Thus, the limitation renders the claims indefinite and clarification is required. As to claim 16, the “depth G” is defined by two oxide arrays 236 and 240 as seen in FIG. 4 of the Drawings. Since claim 9 only defines one oxide array 240, it does not appears “the depth G is between about 1µm and about 3µm” as recited. It is not clear whether “about” encompasses a broader interpretation of the disclosure. Thus, the limitation renders the claim indefinite and clarification is required. As to claim 21, the limitation “the pixel oxide islands” lacks sufficient antecedent basis. Thus, the limitation renders the claims indefinite and clarification is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 9-11, 17-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2014/0264948 A1 to Yang et al. (“Chou”) in view of U.S. Patent Application Publication No. 2018/0069037 A1 to Yang et al. (“Yang”).
As to claim 1, although Chou discloses a package, comprising: a lower die (100); and an upper die (200) that is stacked on top of the lower die (100); and an upper oxide array of raised upper oxide features (210) disposed on a bond side of the upper die (200), wherein the raised upper oxide features (210) extend directly between the upper die (200) and the lower die (100) to contact with the lower die (100) to form a plurality of inner bonds (between 104, 204) and to thereby define a plurality of fluidly connected air gaps (116, 216) between the lower die (100) and the upper die (200), wherein each air gap (116, 216) is a void between an inner region of the upper die (200) and an inner region of the lower die (100) separated in an x- and y- direction by the raised upper oxide features (210), wherein each air gap (116, 216) provides an unobstructed path in a z-direction directly between the upper die (200) and the lower die (100); and a plurality of outer bonds (outside 104, 204) disposed between an outer region of the lower die (100) and an outer region of the upper die (200) (See Fig. 10, Fig. 11, ¶ 0009, ¶ 0011, ¶ 0012, ¶ 0014, ¶ 0016, ¶ 0017, ¶ 0019, ¶ 0021, ¶ 0022, ¶ 0024, ¶ 0025), Chou does not further disclose wherein the package is an image sensor; wherein the lower die is a logic die, comprising a function logic element disposed on a bond side of the logic die; wherein the upper die is a pixel die that is stacked on top of the logic die, the pixel die comprising: a pixel array disposed on a light receiving side of the pixel die; and wherein the upper oxide array of raised upper oxide features disposed on the bond side of the upper die is a pixel oxide array of raised pixel oxide features disposed on a bond side of the pixel die. However, Yang does disclose wherein the package is an image sensor; a lower logic die (205, 210, 220, 230), comprising a function logic element (210) disposed on a bond side of the logic die (205, 210, 220, 230); wherein an upper pixel die (105, 110, 120, 130) that is stacked on top of the logic die (205, 210, 220, 230), the pixel die (105, 110, 120, 130) comprising: a pixel array (pixels ¶ 0056) disposed on a light receiving side of the pixel die (105, 110, 120, 130); and wherein an upper pixel oxide array of raised pixel oxide features (160, 310) disposed on a bond side of the pixel die (105, 110, 120, 130) (See Fig. 2D, Fig. 3, ¶ 0004, ¶ 0055, ¶ 0056, ¶ 0059-¶ 0076, ¶ 0079, ¶ 0080, ¶ 0084, ¶ 0085). In view of the teaching of Yang, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Chou to have wherein the package is an image sensor; wherein the lower die is a logic die, comprising a function logic element disposed on a bond side of the logic die; wherein the upper die is a pixel die that is stacked on top of the logic die, the pixel die comprising: a pixel array disposed on a light receiving side of the pixel die; and wherein the upper oxide array of raised upper oxide features disposed on the bond side of the upper die is a pixel oxide array of raised pixel oxide features disposed on a bond side of the pixel die because the stacked package allows the image sensor to provide signal processing in the lower logic die from sensing signal in the upper pixel die (See ¶ 0004). As to claim 2, Chou in view of Yang further discloses wherein the raised pixel oxide features (210/160, 310) form a plurality of pixel oxide islands (210/160) that are shaped as square, ovular, or circular shapes (See Chou Fig. 11 and Yang Fig. 3, ¶ 0085). As to claim 3, Chou in view of Yang further discloses wherein the pixel oxide islands (210/160) comprise a first pixel oxide island (smaller, square left 210) and a second pixel island (larger, rectangle middle 210), and wherein the first pixel oxide island (smaller, square left 210) and the second pixel island (larger, rectangle middle 210) have different shapes (See Chou Fig. 10). As to claim 9, although Chou discloses a package, comprising: a lower die (100); a lower oxide array of raised lower oxide features (110) disposed on a bond side of the lower die (100); and an upper die (200) that is stacked on top of the lower die (100); wherein the raised lower oxide features (110) extend directly between the upper die (200) and the lower die (100) to contact with the upper die (200) to form a plurality of inner bonds (between 104, 204), and to thereby define a plurality of fluidly connected air gaps (116, 216) between an inner region the lower die (100) and an inner region of the upper die (200), wherein each air gap (116, 216) is a void between the upper die (200) and the lower die (100) separated in an x- and y- direction by the raised lower oxide features (110), wherein each air gap (116, 216) provides an unobstructed path in a z-direction directly between the upper die (200) and the lower die (100); and a plurality of outer bonds (outside 104, 204) disposed between an outer region of the lower die (100) and an outer region of the upper die (200) (See Fig. 10, Fig. 11, ¶ 0009, ¶ 0011, ¶ 0012, ¶ 0014, ¶ 0016, ¶ 0017, ¶ 0019, ¶ 0021, ¶ 0022, ¶ 0024, ¶ 0025), Chou does not further disclose wherein the package is an image sensor; wherein the lower die is a logic die, comprising: a function logic element disposed on a bond side of the logic die; wherein the lower oxide array of raised lower oxide features disposed on the bond side of the lower die is a logic oxide array of raised logic oxide features disposed on the bond side of the logic die; and wherein the upper die is a pixel die that is stacked on top of the logic die, the pixel die comprising: a pixel array disposed on a light receiving side of the pixel die. However, Yang does disclose wherein the package is an image sensor, comprising: a lower logic die (205, 210, 220, 230), comprising: a function logic element (210) disposed on a bond side of the logic die (205, 210, 220, 230); a lower logic oxide array of raised logic oxide features (260, 310) disposed on the bond side of the logic die (205, 210, 220, 230); and an upper pixel die (105, 110, 120, 130) that is stacked on top of the logic die (205, 210, 220, 230), the pixel die (105, 110, 120, 130) comprising: a pixel array (pixels ¶ 0056) disposed on a light receiving side of the pixel die (105, 110, 120, 130) (See Fig. 2D, Fig. 3, ¶ 0004, ¶ 0055, ¶ 0056, ¶ 0059-¶ 0076, ¶ 0079, ¶ 0080, ¶ 0084, ¶ 0085). In view of the teaching of Yang, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Chou to have wherein the package is an image sensor; wherein the lower die is a logic die, comprising: a function logic element disposed on a bond side of the logic die; wherein the lower oxide array of raised lower oxide features disposed on the bond side of the lower die is a logic oxide array of raised logic oxide features disposed on the bond side of the logic die; and wherein the upper die is a pixel die that is stacked on top of the logic die, the pixel die comprising: a pixel array disposed on a light receiving side of the pixel die because the stacked package allows the image sensor to provide signal processing in the lower logic die from sensing signal in the upper pixel die (See ¶ 0004). As to claim 10, Chou in view of Yang further discloses wherein the raised logic oxide features (110/260, 310) form a plurality of logic oxide islands (110/260) that are shaped as square, ovular, or circular shapes (See Chou Fig. 11 and Yang Fig. 3, ¶ 0085). As to claim 11, Chou in view of Yang further discloses wherein the plurality of logic oxide islands (110/160) comprise a first logic oxide island (smaller, square left 110) and a second logic island (larger, rectangle middle 110), and wherein the first logic oxide island (smaller, square left 110) and the second logic island (larger, rectangle middle 110) have different shapes (See Chou Fig. 10). As to claim 17, although Chou discloses a package, comprising: a lower die (100); and a lower oxide array of raised lower oxide features (110) disposed on a bond side of the lower die (100); an upper die (200) that is stacked on top of the lower die (100); and an upper oxide array of raised upper oxide features (210) disposed on a bond side of the upper die (200); a plurality of outer bonds (outside 104, 204) disposed between an outer region of the lower die (100) and an outer region of the upper die (200); and wherein the raised lower oxide features (110) are attached to the lower die (100) at a plurality of inner bonds (between 104, 204) of an inner region of the lower die (100), wherein the raised upper oxide features (210) are attached to the upper die (200) at a plurality of inner bonds (between 104, 204) of an inner region of the upper die (200), and wherein the inner bonds (between 104, 204) are separated from each other and spaced apart in an x- and y-direction by a plurality of fluidly connected air gaps (116, 216) forming a void between the inner region of the lower die (100) and the inner region of the upper die (200), wherein each air gap (116, 216) provides an unobstructed path in a z-direction directly between the upper die (200) and the lower die (100); (See Fig. 10, Fig. 11, ¶ 0009, ¶ 0011, ¶ 0012, ¶ 0014, ¶ 0016, ¶ 0017, ¶ 0019, ¶ 0021, ¶ 0022, ¶ 0024, ¶ 0025), Chou does not further disclose wherein the package is an image sensor; wherein the lower die is a logic die, comprising: a function logic element disposed on a bond side of the logic die; wherein the lower oxide array of raised lower oxide features disposed on the bond side of the lower die is a logic oxide array of raised logic oxide features disposed on the bond side of the logic die; wherein the upper die is a pixel die that is stacked on top of the logic die, the pixel die comprising: a pixel array disposed on a light receiving side of the pixel die; and wherein the upper oxide array of raised upper oxide features disposed on the bond side of the upper die is a pixel oxide array of raised pixel oxide features disposed on a bond side of the pixel die. However, Yang does disclose wherein the package is an image sensor, comprising: a lower logic die (205, 210, 220, 230), comprising: a function logic element (210) disposed on a bond side of the logic die (205, 210, 220, 230); and a lower logic oxide array of raised logic oxide features (260, 310) disposed on the bond side of the logic die (205, 210, 220, 230); an upper pixel die (105, 110, 120, 130) that is stacked on top of the logic die (205, 210, 220, 230), the pixel die (105, 110, 120, 130) comprising: a pixel array (pixels ¶ 0056) disposed on a light receiving side of the pixel die (105, 110, 120, 130); and an upper pixel oxide array of raised pixel oxide features (160, 310) disposed on a bond side of the pixel die (105, 110, 120, 130) (See Fig. 2D, Fig. 3, ¶ 0004, ¶ 0055, ¶ 0056, ¶ 0059-¶ 0076, ¶ 0079, ¶ 0080, ¶ 0084, ¶ 0085) (Notes: In view of the teaching of Yang, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Chou to have wherein the package is an image sensor; wherein the lower die is a logic die, comprising: a function logic element disposed on a bond side of the logic die; wherein the lower oxide array of raised lower oxide features disposed on the bond side of the lower die is a logic oxide array of raised logic oxide features disposed on the bond side of the logic die; wherein the upper die is a pixel die that is stacked on top of the logic die, the pixel die comprising: a pixel array disposed on a light receiving side of the pixel die; and wherein the upper oxide array of raised upper oxide features disposed on the bond side of the upper die is a pixel oxide array of raised pixel oxide features disposed on a bond side of the pixel die because the stacked package allows the image sensor to provide signal processing in the lower logic die from sensing signal in the upper pixel die (See ¶ 0004). As to claim 18, Chou in view of Yang further discloses wherein individual raised logic oxide features (110/260, 310) and individual raised pixel oxide features (210/160, 310) are aligned and contacting each other (See Chou Fig. 10). As to claim 20, Chou in view of Yang further discloses wherein the raised logic oxide features (110/260, 310) and the raised pixel oxide features (210/160, 310) form a plurality of logic oxide islands (110, 210) that are shaped as square, ovular, or circular shapes (See Fig. 10).
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2018/0069037 A1 to Yang et al. (“Yang”) as applied to claim 18 above, and further in view of U.S. Patent Application Publication No. 2018/0175012 A1 to Wu et al. (“Wu”). The teachings of Chou and Yang have been discussed above.
As to claim 19, although Chou and Yang do not further disclose a depth G, Chou and Yang in view of Wu further discloses wherein each raised logic oxide feature (110/260, 310) has a first height and each raised pixel oxide feature (210/160, 310) has a second height, wherein a sum of the first height and the second height equals a depth G (W1), and wherein the depth G (W1) is between about 1 μm and about 3 μm (See Yang Fig. 3, ¶ 0085 and Wu Fig. 1-Fig. 6, ¶ 0024, ¶ 0030), wherein the depth determines how much air is provided in the image sensor to accommodate the metal bonds. Further, the applicant also has not established the critical nature of the “wherein the depth G is between about 1 μm and about 3 μm.” “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims….In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have various ranges. It would also have been obvious to one of ordinary skill in the art at the time the invention was made to discover the optimum dimensions in light of design requirements such as thermal expansion and constraints such as overall device dimensions. See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Response to Arguments
Applicant's arguments with respect to claims 1, 9, and 17 have been considered but are moot in view of the new ground(s) of rejection.
Allowable Subject Matter
Claims 4-5 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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