Prosecution Insights
Last updated: August 16, 2026
Application No. 18/434,981

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Feb 07, 2024
Priority
Feb 22, 2023 — JP 2023-026378
Examiner
GARCES, NELSON Y
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
475 granted / 591 resolved
+12.4% vs TC avg
Minimal +3% lift
Without
With
+2.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
31 currently pending
Career history
634
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
50.6%
+10.6% vs TC avg
§102
32.5%
-7.5% vs TC avg
§112
13.7%
-26.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 591 resolved cases

Office Action

§102
DETAILED ACTION This action is responsive to the application No. 18/434,981 filed on February 07, 2024. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election without traverse of the Species 1 invention reading on Fig. 1 in the reply filed on 05/29/2026 is acknowledged. The Applicants indicated that claims 1-6, 12-14, 16 and 17 read on the elected invention. However, claims 2-4 read on non-elected species of the claimed invention. For instance, claim 2 recites “an intermediate line…”, claim 3 recites “…a ground line…”, these features, however, are exclusive of Species 3. Claims 2-4, 7-11, and 15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected species, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-17. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 5, 6, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishimura (US 6,233,169). Regarding Claim 1, Nishimura (see, e.g., Figs. 1, 3A-3B, 4-6), teaches a semiconductor device comprising: a field effect transistor NT that has a first terminal 24 connected to a load INV1, a second terminal 22 conducting to the first terminal 24 via a channel 26, and a control terminal 30 that controls conduction and interruption of the channel 26 by an electric field (see, e.g., col. 5, ll. 1-30); and a nonvolatile memory Cferro that is a nonvolatile memory connected to the control terminal 30 and has a second control terminal 34 supplied with a voltage that changes a direction of the electric field from the control terminal 30 (see, e.g., col. 5, ll. 31-34, col. 7, ll. 35-47). Regarding Claim 5, Nishimura teaches all aspects of claim 1. Nishimura (see, e.g., Figs. 1, 3A-3B, 4-6), teaches: a semiconductor chip (see, e.g., col. 9, ll. 47-53), wherein: the field effect transistor NT includes a transistor structure that has a first electrode D as the first terminal 24 electrically connected to the semiconductor chip, a second electrode S as the second terminal 22 electrically connected to the semiconductor chip, and a channel control region formed between the first electrode D and the second electrode S (see, e.g., col. 5, ll. 14-25), and the nonvolatile memory Cferro includes a memory structure formed on the semiconductor chip that is in common with the transistor structure NT (see, e.g., col. 7, ll. 26-34). Regarding Claim 6, Nishimura teaches all aspects of claim 5. Nishimura (see, e.g., Figs. 1, 3A-3B, 4-6), teaches that: the memory structure includes a ferroelectric film 32 laminated directly on the channel control region (i.e., 30) and an upper electrode as the second control terminal 34 laminated on the ferroelectric film 32 (see, e.g., col. 5, ll. 26-30), and, due to polarization of the ferroelectric film 32, the polarization being caused by the supply of the voltage to the upper electrode, the direction of the electric field from the channel control region as the control terminal 30 changes, and the conduction and interruption of the channel 26 are controlled. The specific claim limitation that due to polarization of the ferroelectric film, the polarization being caused by the supply of the voltage to the upper electrode, the direction of the electric field from the channel control region as the control terminal changes, and the conduction and interruption of the channel are controlled, is a property of the ferroelectric film of Nishimura’s device. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp.v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985). Since Nishimura teaches all the structural features of the claimed invention, the characteristic polarization of the ferroelectric film is an inherent property of Nishimura’s invention. Regarding Claim 12, Nishimura teaches all aspects of claim 6. Nishimura (see, e.g., Figs. 1, 3A-3B, 4-6), teaches that the ferroelectric film 32 is any one of a single crystal PZT (lead zirconate titanate) thin film, a polycrystalline PZT thin film, and a BST ((Ba, Sr) TiO3) thin film (see, e.g., col. 5, ll. 26-30). Allowable subject matter Claims 13, 14, 16, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571) 272-8249. The examiner can normally be reached on Mon-Fri 9:00 AM-5:30 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy can be reached on (571) 272-1705. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nelson Garces/Primary Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Feb 07, 2024
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
83%
With Interview (+2.9%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 591 resolved cases by this examiner. Grant probability derived from career allowance rate.

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