Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims & Rejoinder
Pursuant to the Director's decision granting Applicant’s Petition under 37 C.F.R. § 1.144, the restriction requirement previously set forth in this application has been withdrawn. Claims 26-35 are hereby rejoined for examination on the merits alongside Claims 1-25 and newly added Claims 36–46. All pending claims (1–46) are examined below in this Non-Final Office Action.
Response to Applicant's Traversal of Rejections Under 35 U.S.C. § 102(a)(1)
Rejection of Claims 1-4, 10-13, and 19-22 over Hao: Applicant maintains that Hao fails to anticipate independent Claims 1, 10, and 19, asserting that element 406 is labeled in Hao as part of its "gate region" rather than its "source region," and that mapping a portion of element 404/406 as a "first subregion" and "second subregion" of differing widths (W_1 and W_2) constitutes an improper re-labeling of Hao’s structure.
Applicant's argument improperly elevates a prior art reference's internal terminology over its physical structural geometry. Under Broad Reasonable Interpretation (BRI), claims in examination are defined by physical structure, spatial relationships, and material boundaries, not by the semantic labels chosen by a reference author.
In Applicant’s own Petition and Remarks filed 6/15/2026, Applicant explicitly argues that all claims across the application describe the exact same underlying physical geometry: "All claims of the application are directed to the same lateral-extended MOSFET structure... A prior art search reasonably tailored to that structure would necessarily encompass all claimed embodiments."
Evaluating the physical, spatial architecture disclosed in Hao’s Figure 6 under BRI, the contiguous semiconductor material exhibits the exact physical dimensions, lateral boundaries, and contiguous subregion interfaces recited in Claims 1, 10, and 19. Segmenting and pointing out that this contiguous physical region possesses a first portion of width W_1 and a second portion of width W_2 directly reads on the structural limitations of the claims. Hao physically anticipates the structural geometry regardless of how Hao labels element 406.
Response to Applicant's Traversal of Rejections Under 35 U.S.C. § 103
Obviousness of Claims 5–9, 14–18, and 23–25 over Hao (and Hao in view of Lin): Applicant argues that the § 103 rejections fail under In re NuVasive because Hao allegedly does not recognize the recited dimensional ratios or subregion width relationships as "result-effective variables" for suppressing parasitic edge effects.
This argument is contradicted by Applicant’s explicit admissions on the record. Applicant repeatedly contends that the unified, overarching purpose of the claimed structural architecture is "addressing the same problem (the subthreshold hump effect attributable to parasitic edge transistors)".
Where a prior art reference (Hao) explicitly discloses a modified, non-uniform active/gate geometry at the device edge to address edge effects, adjusting the specific physical lengths, widths, and dimensional ratios of those contiguous regions constitutes routine parameter optimization under MPEP § 2144.05. A person of ordinary skill in the art (POSITA) seeking to suppress parasitic edge transistors, a problem known in the art and addressed by Hao, would naturally optimize these physical dimensions to achieve desired electrical performance. The motivation is grounded in the physical reality of edge-effect suppression disclosed in Hao, satisfying the requirements of In re NuVasive.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 35 rejected under 35 U.S.C. 101 because claim 35 recites "A computer program product for implementing a semiconductor structure... said computer program product further comprising computer readable program code for describing the semiconductor structure."
Non-functional descriptive material, such as computer program code or data structures per se that merely encode or describe a physical structure without being integrated into a practical application or tangible manufacturing process, is non-statutory under 35 U.S.C. 101 (see MPEP § 2106.03). The claim does not recite any physical apparatus execution, specialized hardware, or process steps that alter the underlying data. Because the computer program product merely stores descriptive data/layout code representing the device of Claim 1, it constitutes a non-statutory abstract data representation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 10-13, 19-22, 36-38 and 41-45 is/are rejected under 35 U.S.C. 102(a)(1) as being by anticipated by Hao et al. (US 20170222012 A1).
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CLAIM 1. Hao teaches the semiconductor structure comprising: a substrate 200; an active region formed on the substrate 200;
a gate region 403 extended over the active region along a first direction parallel to a surface of the substrate; and a source region 404 formed within the active region 401 and adjacent to the gate region 403 in a second direction parallel to the surface and perpendicular to the first direction,
wherein:
the source region 404 comprises a first subregion 404 and a second subregion (D2 portion of 404) such that the second subregion is between the first subregion and the gate region 403;
the first subregion comprises a first width along the first direction and the second subregion comprises a second width along the first direction; and the first width is less than the second width (See mark-up of Fig. 6 below & Abstract1).
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CLAIM 2. Hao teaches the semiconductor structure of claim 1, further comprising a channel region formed in the active region between the substrate and the gate region, wherein: the channel region has a channel width along the first direction; and the channel width is substantially equal to the second width (Hao Fig. 6).
CLAIM 3. Hao teaches the semiconductor structure of claim 1, wherein: the second subregion comprises a length along the second direction; the second subregion extends beyond the first subregion by a third width along the first direction; and the length is less than or equal to the third width (Hao Fig. 6).
CLAIM 4. Hao teaches the semiconductor structure of claim 1, wherein: the first subregion comprises a first length along the second direction; the second subregion comprises a second length D2 along the second direction; and the second length is less than the first length (Hao Fig. 6).
CLAIM 10. Hao teaches a integrated circuit comprising: a substrate;
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and a transistor over the substrate 200 comprising:
an active region 401 formed on the substrate;
a gate region 402 extended over the active region along a first direction parallel to a surface of the substrate (Hao Fig 6); and
a source region 402 formed within the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction, wherein:
the source region comprises a first subregion and a second subregion such that the second subregion D1 is between the first subregion and the gate region (Fig. 6);
the first subregion comprises a first width along the first direction and the second subregion comprises a second width along the first direction; and the first width is less than the second width (Hao Fig. 6 – See Mark-up regarding Claim 1.).
CLAIM 11. Hao teaches the integrated circuit of claim 10, wherein the transistor further comprises a channel region formed in the active region, wherein: the channel region has a channel width along the first direction; and the channel width is substantially equal to the second width (Hao Fig. 6).
CLAIM 12. Hao teaches the integrated circuit of claim 10, wherein: the second subregion comprises a length along the second direction; the second subregion extends beyond the first subregion by a third width along the first direction; and the length is less than or equal to the third width (Hao Fig. 6).
CLAIM 13. Hao teaches the integrated circuit of claim 10, wherein: the first subregion comprises a first length along the second direction; the second subregion comprises a second length along the second direction; and the second length is less than the first length (Hao Fig. 6).
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CLAIM 19. Hao teaches a semiconductor chip, comprising:
a substrate 200;
a first active region 404 (Fig. 7) having a first width along a first direction parallel to a surface of the substrate (Figs. 6&7);
a gate 402 extended over the first active region along the first direction; and a second active region 403 (Fig. 7) formed on the surface adjacent to a first oxide diffusion region 205 (i.e. Fig. 4F) and having a second width shorter than the first width along the first direction (Hao Fig. 6&7 & Abstract)..
CLAIM 20. Hao teaches the semiconductor chip of claim 19, further comprising a channel region formed in the first active region between the surface and the gate, wherein: the channel region has a channel width along the first direction; and the channel width is substantially equal to the first width (Hao Fig. 6&7 & Abstract).
CLAIM 21. Hao teaches the semiconductor chip of claim 19, wherein: the first active region comprises a length along a second direction; the first active region extends beyond the second active region by a third width along the first direction; and the length is less than or equal to the third width (Hao Fig. 6&7 & Abstract)...
CLAIM 22. Hao teaches the semiconductor chip of claim 19, wherein: the first active region comprises a first length along a second direction; the second active region comprises a second length along the second direction; and the first length is less than the second length (Hao Fig. 6&7 & Abstract).
CLAIM 36. Hao teaches the semiconductor structure of claim 1, wherein the first subregion and the second subregion are contiguous doped portions of the source region (source region 404), the second subregion abutting the gate region 403 along the second direction (Hao Fig. 6).
CLAIM 37. Hao teaches the semiconductor structure of claim 36, further comprising a channel region formed in the active region between the substrate and the gate region, wherein the second width is substantially equal to a channel width of the channel region along the first direction (Hao Fig. 6).
CLAIM 38. Hao teaches the semiconductor structure of claim 36, wherein the first subregion and the second subregion define a step in a lateral edge of the source region along the first direction, such that the source region is narrower along the first direction at the first subregion than at the second subregion (Hao Fig. 6).
CLAIM 41. Hao teaches the integrated circuit of claim 10, wherein the first subregion and the second subregion are contiguous doped portions of the source region (source region 404), the second subregion abutting the gate region 403 along the second direction, and wherein the second width is substantially equal to a channel width of a channel region underlying the gate region along the first direction (Hao Fig. 6).
CLAIM 42. Hao teaches the integrated circuit of claim 41, wherein the first subregion and the second subregion define a step in a lateral edge of the source region along the first direction, such that the source region is narrower along the first direction at the first subregion than at the second subregion (Hao Fig. 6).
CLAIM 44. Hao teaches the semiconductor chip of claim 19, wherein the first active region and the second active region are contiguous portions of a single source region of a single transistor, the second active region abutting the gate along the second direction (Hao Figs. 6 & 7).
CLAIM 45. Hao teaches the semiconductor chip of claim 44, wherein the first active region and the second active region define a step in a lateral edge of the source region along the first direction, such that the source region is narrower along the first direction at the first active region than at the second active region, and wherein the second width is substantially equal to a channel width of a channel region underlying the gate along the first direction (Hao Figs. 6 & 7).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-9, 14-15, 17-18, 23-25 26-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hao et al. (US 20170222012 A1).
CLAIM 5. Hao teaches the semiconductor structure of claim 1, wherein: the first subregion comprises a first length along the second direction; the second subregion comprises a second length D2 along the second direction (Hao Fig. 6); however may be silent upon wherein a first ratio of the first length to the first width is less than or equal to a second ratio of the second width to the second length.
Hao discloses a semiconductor device structure with an active region (labeled as 403, 404, 405 in Fig. 6) that possesses a non-uniform width, matching the shape described in the present claim. Furthermore, this structure serves the same purpose as that described in the applicant’s specification: mitigating the subthreshold hump caused by parasitic edge transistors (Hao ¶54).
While Hao explicitly discusses optimizing specific lengths (D1, D2), the entire, complex, non-uniform geometry disclosed constitutes a result-effective variable. A Person Having Ordinary Skill In The Art (POSITA) would recognize that manipulating the widths of this active region is necessary to effectively suppress parasitic edge effects. Therefore, the claimed dimensions and dimensional relationships are merely "optimizable parameters".
Finding the optimum relative values or relational rules for this known, non-uniform shape shown in Hao’s Figure 6 constitutes routine optimization rather than an inventive contribution. The claimed structure (the shape and arrangement between the gate line and active area) is visually identical and offers no distinguishable structural features over Hao, representing only new descriptive language.
Therefore, it would have been obvious to a POSITA to determine the workable or optimal lengths, widths, and ratios thereof through routine experimentation to achieve desired device performance. As these dimensions are result-effective variables and there is no evidence that the claimed ranges are critical or produce unexpected results, the subject matter is obvious over Hao. See MPEP § 2144.05.
CLAIM 6. Hao teaches the semiconductor structure of claim 1, further comprising a drain region formed in the active structure and adjacent to the gate region in the second direction, wherein: the gate region is between the source region and the drain region; the drain region comprises a third subregion and a fourth subregion; the fourth subregion is between the third subregion and the gate region; the third subregion comprises a third width along the first direction and the fourth subregion comprises a fourth width along the first direction; and the third width is less than the fourth width (Hao Fig. 6- Illustrates a transistor with a dual-section drain region where a larger-width section is connected to the channel through a smaller-width section, representing standard source/drain engineering, and therefore, optimizing the specific width ratios between these adjacent subregions to enhance performance is a matter of routine optimization within the skill of a POSITA.).
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CLAIM 8. Hao teaches the semiconductor structure of claim 1, wherein: the source region further comprises a third subregion; wherein the third subregion is between the first subregion and the second subregion; the first subregion comprises a first width along the first direction and the second subregion comprises a second width along the first direction and the third subregion comprises a third width along the first direction; and the first width is less than the third width and the third width is less than the second width (Hao Fig. 6- Illustrates a transistor with a dual-section drain region where a larger-width section is connected to the channel through a smaller-width section, representing standard source/drain engineering, and therefore, optimizing the specific width ratios between these adjacent subregions to enhance performance is a matter of routine optimization within the skill of a POSITA.).
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CLAIM 9. Hao teaches the semiconductor structure of claim 8 wherein at least one of the first subregion and the third subregion form a tapered shape in which width of such region varies in the first direction (Hao Fig. 6- Illustrates a transistor with a dual-section drain region where a larger-width section is connected to the channel through a smaller-width section, representing standard source/drain engineering, and therefore, optimizing the specific width ratios between these adjacent subregions to enhance performance is a matter of routine optimization within the skill of a POSITA.).
CLAIM 14. Hao teaches the integrated circuit of claim 10, wherein: the first subregion comprises a first length along the second direction; the second subregion comprises a second length along the second direction (Hao Fig. 6); however may be silent upon wherein a first ratio of the first length to the first width is less than or equal to a second ratio of the second width to the second length.
Hao discloses a semiconductor device structure with an active region (labeled as 403, 404, 405 in Fig. 6) that possesses a non-uniform width, matching the shape described in the present claim. Furthermore, this structure serves the same purpose as that described in the applicant’s specification: mitigating the subthreshold hump caused by parasitic edge transistors (Hao ¶54).
While Hao explicitly discusses optimizing specific lengths (D1, D2), the entire, complex, non-uniform geometry disclosed constitutes a result-effective variable. A Person Having Ordinary Skill In The Art (POSITA) would recognize that manipulating the widths of this active region is necessary to effectively suppress parasitic edge effects. Therefore, the claimed dimensions and dimensional relationships are merely "optimizable parameters".
Finding the optimum relative values or relational rules for this known, non-uniform shape shown in Hao’s Figure 6 constitutes routine optimization rather than an inventive contribution. The claimed structure (the shape and arrangement between the gate line and active area) is visually identical and offers no distinguishable structural features over Hao, representing only new descriptive language.
Therefore, it would have been obvious to a POSITA to determine the workable or optimal lengths, widths, and ratios thereof through routine experimentation to achieve desired device performance. As these dimensions are result-effective variables and there is no evidence that the claimed ranges are critical or produce unexpected results, the subject matter is obvious over Hao. See MPEP § 2144.05.
CLAIM 15. Hao teaches the integrated circuit of claim 10, wherein the transistor further comprises a drain region formed in the active region and adjacent to the gate region in the second direction, wherein: the gate region is between the source region and the drain region; the drain region comprises a third subregion and a fourth subregion; the fourth subregion is between the third subregion and the gate region; the third subregion comprises a third width along the first direction and the fourth subregion comprises a fourth width along the first direction; and the third width is less than the fourth width (Hao Fig. 6- Illustrates a transistor with a dual-section drain region where a larger-width section is connected to the channel through a smaller-width section, representing standard source/drain engineering, and therefore, optimizing the specific width ratios between these adjacent subregions to enhance performance is a matter of routine optimization within the skill of a POSITA.).
CLAIM 17. Hao teaches the integrated circuit of claim 10, wherein: the source region further comprises a third subregion; wherein the third subregion is between the first subregion and the second subregion; the first subregion comprises a first width along the first direction and the second subregion comprises a second width along the first direction and the third subregion comprises a third width along the first direction; and the first width is less than the third width and the third width is less than the second width (Hao Fig. 6- Illustrates a transistor with a dual-section drain region where a larger-width section is connected to the channel through a smaller-width section, representing standard source/drain engineering, and therefore, optimizing the specific width ratios between these adjacent subregions to enhance performance is a matter of routine optimization within the skill of a POSITA.).
CLAIM 18. Hao teaches the integrated circuit of claim 17 wherein at least one of the first subregion and the third subregion form a tapered shape in which width of such region varies in the first direction (Hao Fig. 6- Illustrates a transistor with a dual-section drain region where a larger-width section is connected to the channel through a smaller-width section, representing standard source/drain engineering, and therefore, optimizing the specific width ratios between these adjacent subregions to enhance performance is a matter of routine optimization within the skill of a POSITA.).
CLAIM 23. Hao teaches the semiconductor chip of claim 19, wherein: the first oxide diffusion region comprises a first length along a second direction; a second oxide diffusion region comprises a second length along the second direction (Hao Fig. 4F, 6 & 7- The dimensions of the components match the length and width of the active layer surfaces they interface with.); however, may be silent upon wherein a first ratio of the first length to the first width is greater than or equal to a second ratio of the second width to the second length.
Hao discloses a semiconductor device structure with an active region (labeled as 403, 404, 405 in Fig. 6) that possesses a non-uniform width, matching the shape described in the present claim. Furthermore, this structure serves the same purpose as that described in the applicant’s specification: mitigating the subthreshold hump caused by parasitic edge transistors (Hao ¶54).
While Hao explicitly discusses optimizing specific lengths (D1, D2), the entire, complex, non-uniform geometry disclosed constitutes a result-effective variable. A Person Having Ordinary Skill In The Art (POSITA) would recognize that manipulating the widths of this active region is necessary to effectively suppress parasitic edge effects. Therefore, the claimed dimensions and dimensional relationships are merely "optimizable parameters".
Finding the optimum relative values or relational rules for this known, non-uniform shape shown in Hao’s Figure 6 constitutes routine optimization rather than an inventive contribution. The claimed structure (the shape and arrangement between the gate line and active area) is visually identical and offers no distinguishable structural features over Hao, representing only new descriptive language.
Therefore, it would have been obvious to a POSITA to determine the workable or optimal lengths, widths, and ratios thereof through routine experimentation to achieve desired device performance. As these dimensions are result-effective variables and there is no evidence that the claimed ranges are critical or produce unexpected results, the subject matter is obvious over Hao. See MPEP § 2144.05.
CLAIM 24. Hao teaches the semiconductor chip of claim 23, further comprising a third oxide diffusion region formed on the surface adjacent to the second oxide diffusion region and having a third width shorter than the second width along the first direction (Hao Fig. 6- Illustrates a transistor with a dual-section drain region where a larger-width section is connected to the channel through a smaller-width section, representing standard source/drain engineering, and therefore, optimizing the specific width ratios between these adjacent subregions to enhance performance is a matter of routine optimization within the skill of a POSITA.).
CLAIM 25. Hao teaches the semiconductor chip of claim 24, wherein at least one of the second oxide diffusion region and the third oxide diffusion region form a tapered shape in which width of such region varies in the first direction (Hao Fig. 6&7)
Claim(s) 7 & 16, 26-35 39, 40, 43, and 46 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hao et al. (US 20170222012 A1) in view of Lin et al. (US 11424339 B2)
CLAIM 7. Hao teaches the semiconductor structure of claim 1, however is silent upon wherein: a first portion of the gate structure has a first doping and a second portion of the gate structure has a second doping; and the first doping is different from the second doping.
Lin teaches a device structure analogous to that claimed, including a similarly shaped active region and overlying gate line. Lin teaches that it was known in the art that gate electrodes could have portions with different doping concentrations [1].
Specifically, Lin’s Figures 4A and 4B depict a gate 120 having a first doped region 122 and distinct non-doped regions 124, resulting in portions with different doping profiles. Lin states:
"As shown in top view 1300 of FIG. 4A, cross-sectional view 1322 of FIG. 4B... a first doped region 122 is formed in the poly gate electrode 120... the poly gate electrode 120 has non-doped regions 124 passing opposing sides of the channel region 104b remaining un-doped after forming the first doped region 122. The non-doped regions 124 are separate and distinct segments."
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It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the gate of Hao with Lin's specific doping technique/structure, since applying a known technique (varying gate doping) to a known device ready for improvement Hao to yield predictable results (transistor performance adjustment) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385).
CLAIM 16. Hao teaches the integrated circuit of claim 10, however is silent upon however is silent upon wherein: a first portion of the gate region has a first doping and a second portion of the gate region has a second doping; and the first doping is different from the second doping.
Lin teaches a device structure analogous to that claimed, including a similarly shaped active region and overlying gate line. Lin teaches that it was known in the art that gate electrodes could have portions with different doping concentrations [1].
Specifically, Lin’s Figures 4A and 4B depict a gate 120 having a first doped region 122 and distinct non-doped regions 124, resulting in portions with different doping profiles. Lin states:
"As shown in top view 1300 of FIG. 4A, cross-sectional view 1322 of FIG. 4B... a first doped region 122 is formed in the poly gate electrode 120... the poly gate electrode 120 has non-doped regions 124 passing opposing sides of the channel region 104b remaining un-doped after forming the first doped region 122. The non-doped regions 124 are separate and distinct segments."
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It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the gate of Hao with Lin's specific doping technique/structure, since applying a known technique (varying gate doping) to a known device ready for improvement Hao to yield predictable results (transistor performance adjustment) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385).
CLAIM 26. Hao teaches the teaches method comprising: forming an active region on a substrate; forming a gate region extended over the active region along a first direction parallel to a surface of the substrate; and forming a source region within the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction, wherein: the source region comprises a first subregion and a second subregion such that the second subregion is between the first subregion and the gate region; the first subregion comprises a first width along the first direction and the second subregion comprises a second width along the first direction; and the first width is less than the second width (See regarding claim 1, the claim merely recites convention manufacturing actions (e.g. forming) the structure as addressed in the rejected claim. Because the resulting physical structure is anticipated by or obvious over the prior art as detailed above regarding device claims 1-25, performing routine well-known semiconductor fabrication operations to produce that identical physical structure constitutes an obvious method of manufacturing under 33 U.S.C 103. Furthermore, as Applicant explicitly noted in the record (e.g. in Applicant’s Petition and associated remarks) that the method claims are not constrained by a specific order of steps, carrying out these conventional fabrication steps in any workable sequence to yield the prior art structure would have been obvious to a person of ordinary skill in the art.)
CLAIM 27. Hao teaches the method of Claim 26, further forming a channel region in the active region between the substrate and the gate region, wherein: the channel region has a channel width along the first direction; and the channel width is substantially equal to the second width (See regarding claim 2, the claim merely recites convention manufacturing actions (e.g. forming) the structure as addressed in the rejected claim. Because the resulting physical structure is anticipated by or obvious over the prior art as detailed above regarding device claims 1-25, performing routine well-known semiconductor fabrication operations to produce that identical physical structure constitutes an obvious method of manufacturing under 33 U.S.C 103. Furthermore, as Applicant explicitly noted in the record (e.g. in Applicant’s Petition and associated remarks) that the method claims are not constrained by a specific order of steps, carrying out these conventional fabrication steps in any workable sequence to yield the prior art structure would have been obvious to a person of ordinary skill in the art.)
CLAIM 28. Hao teaches the method of Claim 26, wherein: the second subregion comprises a length along the second direction; the second subregion extends beyond the first subregion by a third width along the first direction; and the length is less than or equal to the third width (See regarding claim 3, the claim merely recites convention manufacturing actions (e.g. forming) the structure as addressed in the rejected claim. Because the resulting physical structure is anticipated by or obvious over the prior art as detailed above regarding device claims 1-25, performing routine well-known semiconductor fabrication operations to produce that identical physical structure constitutes an obvious method of manufacturing under 33 U.S.C 103. Furthermore, as Applicant explicitly noted in the record (e.g. in Applicant’s Petition and associated remarks) that the method claims are not constrained by a specific order of steps, carrying out these conventional fabrication steps in any workable sequence to yield the prior art structure would have been obvious to a person of ordinary skill in the art.)
CLAIM 29. Hao teaches the method of Claim 26, wherein: the first subregion comprises a first length along the second direction; the second subregion comprises a second length along the second direction; and the second length is less than the first length (See regarding claim 4, the claim merely recites convention manufacturing actions (e.g. forming) the structure as addressed in the rejected claim. Because the resulting physical structure is anticipated by or obvious over the prior art as detailed above regarding device claims 1-25, performing routine well-known semiconductor fabrication operations to produce that identical physical structure constitutes an obvious method of manufacturing under 33 U.S.C 103. Furthermore, as Applicant explicitly noted in the record (e.g. in Applicant’s Petition and associated remarks) that the method claims are not constrained by a specific order of steps, carrying out these conventional fabrication steps in any workable sequence to yield the prior art structure would have been obvious to a person of ordinary skill in the art.)
CLAIM 30. Hao teaches the method of Claim 26, wherein: the first subregion comprises a first length along the second direction; the second subregion comprises a second length along the second direction; and wherein a first ratio of the first length to the first width is less than or equal to a second ratio of the second width to the second length (See regarding claim 5, the claim merely recites convention manufacturing actions (e.g. forming) the structure as addressed in the rejected claim. Because the resulting physical structure is anticipated by or obvious over the prior art as detailed above regarding device claims 1-25, performing routine well-known semiconductor fabrication operations to produce that identical physical structure constitutes an obvious method of manufacturing under 33 U.S.C 103. Furthermore, as Applicant explicitly noted in the record (e.g. in Applicant’s Petition and associated remarks) that the method claims are not constrained by a specific order of steps, carrying out these conventional fabrication steps in any workable sequence to yield the prior art structure would have been obvious to a person of ordinary skill in the art.)
CLAIM 31. Hao teaches the method of Claim 26, further comprising forming a drain region in the active region and adjacent to the gate region in the second direction, wherein: the gate region is between the source region and the drain region; the drain region comprises a third subregion and a fourth subregion; the fourth subregion is between the third subregion and the gate region; the third subregion comprises a third width along the first direction and the fourth subregion comprises a fourth width along the first direction; and the third width is less than the fourth width (See regarding claim 6, the claim merely recites convention manufacturing actions (e.g. forming) the structure as addressed in the rejected claim. Because the resulting physical structure is anticipated by or obvious over the prior art as detailed above regarding device claims 1-25, performing routine well-known semiconductor fabrication operations to produce that identical physical structure constitutes an obvious method of manufacturing under 33 U.S.C 103. Furthermore, as Applicant explicitly noted in the record (e.g. in Applicant’s Petition and associated remarks) that the method claims are not constrained by a specific order of steps, carrying out these conventional fabrication steps in any workable sequence to yield the prior art structure would have been obvious to a person of ordinary skill in the art.)
CLAIM 32. Hao teaches the method of Claim 26, wherein: a first portion of the gate region has a first doping and a second portion of the gate region has a second doping; and the first doping is different from the second doping (See regarding claim 7, the claim merely recites convention manufacturing actions (e.g. forming) the structure as addressed in the rejected claim. Because the resulting physical structure is anticipated by or obvious over the prior art as detailed above regarding device claims 1-25, performing routine well-known semiconductor fabrication operations to produce that identical physical structure constitutes an obvious method of manufacturing under 33 U.S.C 103. Furthermore, as Applicant explicitly noted in the record (e.g. in Applicant’s Petition and associated remarks) that the method claims are not constrained by a specific order of steps, carrying out these conventional fabrication steps in any workable sequence to yield the prior art structure would have been obvious to a person of ordinary skill in the art.)
CLAIM 33. Hao teaches the method of Claim 26, wherein: the source region further comprises a third subregion; wherein the third subregion is between the first subregion and the second subregion; the first subregion comprises a first width along the first direction and the second subregion comprises a second width along the first direction and the third subregion comprises a third width along the first direction; and the first width is less than the third width and the third width is less than the second width (See regarding claim 8, the claim merely recites convention manufacturing actions (e.g. forming) the structure as addressed in the rejected claim. Because the resulting physical structure is anticipated by or obvious over the prior art as detailed above regarding device claims 1-25, performing routine well-known semiconductor fabrication operations to produce that identical physical structure constitutes an obvious method of manufacturing under 33 U.S.C 103. Furthermore, as Applicant explicitly noted in the record (e.g. in Applicant’s Petition and associated remarks) that the method claims are not constrained by a specific order of steps, carrying out these conventional fabrication steps in any workable sequence to yield the prior art structure would have been obvious to a person of ordinary skill in the art.)
CLAIM 34. Hao teaches the method of Claim 33 wherein at least one of the first subregion and the third subregion form a tapered shape in which width of such region varies in the first direction (See regarding claim 9, the claim merely recites convention manufacturing actions (e.g. forming) the structure as addressed in the rejected claim. Because the resulting physical structure is anticipated by or obvious over the prior art as detailed above regarding device claims 1-25, performing routine well-known semiconductor fabrication operations to produce that identical physical structure constitutes an obvious method of manufacturing under 33 U.S.C 103. Furthermore, as Applicant explicitly noted in the record (e.g. in Applicant’s Petition and associated remarks) that the method claims are not constrained by a specific order of steps, carrying out these conventional fabrication steps in any workable sequence to yield the prior art structure would have been obvious to a person of ordinary skill in the art.)
CLAIM 35. Hao teaches the computer program product for implementing a semiconductor structure comprising a substrate, an active region formed on the substrate, a gate region extended over the active region along a first direction parallel to a surface of the substrate, and a source region formed within the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction, wherein the source region comprises a first subregion and a second subregion such that the second subregion is between the first subregion and the gate region, the first subregion comprises a first width along the first direction and the second subregion comprises a second width along the first direction, and the first width is less than the second width, the computer program product comprising a computer usable medium having computer readable code physically embodied therein, said computer program product further comprising computer readable program code for describing the semiconductor structure (See regarding claim 1, the claim merely recites expressing or encoding the structural features of Claim 1 in a computer program product format. As established above regarding device Claims 1–4, the underlying physical semiconductor structure—comprising the substrate, active region, gate region, and source subregions (W_1 < W_2)—is anticipated by Hao under 35 U.S.C. 102(a)(1).)
To the extent that Claim 35 recites a computer program product comprising code for describing this structure, encoding or storing the structural coordinates and layout details of a known prior art semiconductor device (Hao) into standard computer-readable code or software format is a routine, conventional implementation. Generating CAD data, layout designs, or computer-readable code to describe a physical semiconductor structure, or even simply a digital photo or picture is well-known in the art of microelectronic fabrication and design. It would have been obvious to a POSITA to express the physical structural parameters disclosed in Hao within a standard computer program product.
CLAIM 39. Hao teaches the semiconductor structure of claim 5. Hao does not explicitly recite that the first ratio and second ratio are selected such that a sheet resistance presented along an edge path of a parasitic transistor exceeds a sheet resistance of a channel region. However, modifying dimensions to achieve a targeted sheet resistance along edge paths represents routine optimization of result-effective variables (MPEP § 2144.05) to suppress parasitic edge transistors, as disclosed in Hao. It would have been obvious to a POSITA to select the claimed dimensional ratios to achieve this desired electrical performance.
CLAIM 40. Hao in view of Lin teaches the semiconductor structure of claim 7 (differential gate doping). Regarding positioning the second portion of the gate region over the second subregion and the first portion over a channel region along a third direction perpendicular to the substrate surface, configuring physical layer overlays to align with corresponding device subregions is a standard geometric arrangement inherent to forming differential gate doping structures. It would have been obvious to a POSITA to position the gate portions as claimed to optimize edge transistor threshold adjustments.
CLAIM 43. Hao in view of Lin teaches the integrated circuit of claim 16. For the reasons set forth in Claim 40 above, positioning the second portion of the gate region over the second subregion and the first portion over a channel region along a third direction perpendicular to the surface of the substrate is obvious under 35 U.S.C. 103.
CLAIM 46. Hao teaches the semiconductor chip of claim 23. For the reasons set forth in Claim 39 above, selecting the first and second ratios such that the sheet resistance presented along an edge path of a parasitic transistor adjacent to an isolation region exceeds a sheet resistance of a channel region underlying the gate constitutes routine optimization of result-effective physical dimensions under 35 U.S.C. 103.
Conclusion
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
9/10/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Hao et al. – Abstract - A manufacturing method for a semiconductor device is provided. The method comprises: providing a semiconductor substrate (200); sequentially forming an oxide layer (201) and a silicon nitride layer (202) on the semiconductor substrate (200); annealing the silicon nitride layer (202), and then etching an active region (401) by using the silicon nitride layer (202) as a mask, so as to form in the semiconductor substrate (200) a trench (203) for filling an isolation material, wherein the active region (401) comprises a gate region (403) and a source region (404) and a drain region (405) that are respectively located on two sides of the gate region (403), and the gate region (403) comprises a body part connected to the source region (404) and the drain region (405) and a protruding part (406) that protrudes and extends from the body part to the trench; etching-back the silicon nitride layer (202) and forming a lining oxide layer (201) on the sidewall and the bottom of the trench; depositing an isolation material layer (205) to fill the trench; grinding the isolation material layer (205) until the top of the silicon nitride layer (202) is exposed; and etching to remove the silicon nitride layer (202).
Prosecution Insights