DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449. The information disclosed therein was considered.
Election/Restrictions
Applicant's election with traverse of species ‘f’ (figure 5) and ‘b’ (figure 2c) in the reply filed on 1/2/26 (and follow-up conversation with Mr. Mclure) is acknowledged.
Based on the art now of record, the Examiner has determined the embodiments to be obvious variants of the genus embodiment and therefore withdraws the requirement pending potential amendments by Applicant in follow-up to the Action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite a “four-array-side edge”. It is not clear what structure is referenced by this term. The specification discusses this term but does not clarify. For example, the disclosure in paragraph 0049 recites: “the 2D memory array 111 is a square array having a four-array-side edge, wherein the four-array-side edge has a plurality of array sides. In other words, the 2D memory array 111 comprises an array side formed by memory cells G11-G13, an array side formed by memory cells G31-G33, an array side formed by memory cells G11, G21 and G31, and an array side formed by memory cells G13, G23 and G33”. It not clear how an edge has four sides—an edge being generally understood to comprise a single dimension. For examination purposes, the claims are interpreted consistent with the Figures (e.g. Figure 5, the elected embodiment) as much as possible (see further rejections below).
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention
The claims are directed to various configurations of divided (first and second) input and output circuits at various positions relative to a three-dimensional memory array. The Examiner finds the written description of these features lacking. There is no description of how such circuits are connected to cells for performing the claimed functions/steps. The claims are also drawn to the physical placement of structures relative to each other (i.e. encoder circuit relative to the sub-arrays of 111). In support of this, the disclosure does illustrate any of the physical connections (e.g. routing of signals in the various embodiments of Figures 2-7) which are necessary to show possession of the full scope of the claims.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. As noted above, the description of the claimed features is lacking and one of ordinary skill would not be able to practice the claimed invention without undue experimentation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 2022/0398439).
Regarding claims 1 and 8, inasmuch as understood, Zhang discloses a three-dimensional memory device, comprising: a 3D memory array (see Figure 28), comprising a plurality of two-dimensional memory arrays (planes of memory cells), and configured to receive a plurality of input voltages (via 2810 and/or 2820) and output a plurality of output currents (via 2850), wherein each of the plurality of 2D memory arrays comprises a plurality of memory cells and comprises a four-array-side edge (four sides); an encoding circuit (see paragraph 0144), coupled to the four-array-side edge and configured to input the plurality of input voltages to the plurality of 2D memory arrays (via 2810 or 2810); a sensing circuit (2850), coupled to the four-array-side edge and configured to receive the plurality of output currents from the plurality of 2D memory arrays; and a processing circuit, coupled to the encoding circuit and the sensing circuit, and configured to perform an in-memory-computing according to the plurality of input voltages and the plurality of output currents (see paragraphs 0111-0114), wherein the four-array-side edge has a plurality of array sides, wherein when one of the plurality of array sides is configured to receive the plurality of input voltages (see Figure 28, connected to 2810 or 2820), another of the plurality of array sides is configured to output the plurality of output currents (see Figure 28, connected to 2850), and the one of the plurality of array sides is not parallel to the another of the plurality of array sides (3 dimensional array, has orthogonal sides as well as parallel).
Claim 15 recites substantially the same features as above but in the form of method steps and is rejected on the same basis.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The remaining cited and attached references teach various embodiments of compute in memory configurations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS KING/Primary Examiner, Art Unit 2824