Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being unpatentable over US20140312491A1; Jin et al.; (hereinafter “Jin”).
Regarding Claim 20 (currently amended), Jin teaches a semiconductor package (#2390a-e, Figures 19A-E) comprising:
a first semiconductor chip (#2300a); and
a second semiconductor chip (#2300b) on the first semiconductor chip,
wherein the first semiconductor chip (#2300a/#190h, Figure 11B, [0231]) includes
a body (#150) having a front surface (#150fs) and a rear surface (#150bs);
a wiring structure (wiring line #118a/b and insulating layer #121) above the front surface of the body (#150fs);
a through via (#115) penetrating the body (#150), and the through via being connected to the wiring structure (#118a),
a heat dissipation structure ([0170-0173]) above the rear surface of the body (#150bs), and the heat dissipation structure including a conductive layer (#164/#166g) connected to the through via (#115), and
a signal pad (#164io) and at least one heat dissipation pad (#166g_g) on the heat dissipation structure, and the signal pad and the heat dissipation pad being connected to the conductive layer ([0172], support portions #166g_1/#166g_2 can continuously connect conductive patterns #164/#166g),
wherein the signal pad and the heat dissipation pad of the first semiconductor chip face the second semiconductor chip (Figures 19A-E, [0178], backside conductive pads connect the chips in the stack).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5-8 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over US20210313254A1; Chen et al.; (hereinafter “Chen”) in view of US20220165643A1; Son et al.; (hereinafter “Son”)
Regarding Claim 1 (currently amended), Chen teaches a semiconductor chip (#100, Figure 6 of Chen annotated, [0039]) comprising:
a body (#102) having a front surface and a rear surface;
a wiring structure (#116) above the front surface of the body;
a through via (#115) penetrating the body (#102), and the through via being connected to the wiring structure (#116);
a heat dissipation structure (Figure 6 of Chen annotated, a conductive structure comprises conductive pads #506 and metal features #124 connecting to electrical devices through via #115, although not explicitly disclosed, it is well known in electrical structure to use metal conductive element for signal/power routing and thermal management) above the rear surface of the body (#102), and the heat dissipation structure including a conductive layer (#124) connected to the through via (#115); and
a signal pad and at least one heat dissipation pad (#506) on the heat dissipation structure, and the signal pad and the at least one heat dissipation pad being connected to the conductive layer (#124).
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Chen does not explicitly teach the signal pad includes at least one of a power pad and a ground pad.
However, Son teaches a semiconductor chip ([0005], Figure 1), comprising a signal pad includes at least one of a power pad and a ground pad ([0026-0027], rear connection electrode #140 includes power rear connection electrode #140P).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Chen with the teaching of Son in order to supply various levels of power voltages or ground voltage required to drive the semiconductor chip according to Son, [0026] or [0037].
Regarding Claim 3, Chen in view of Son teaches the semiconductor chip as described in claim 1, wherein Chen further teaches the conductive layer includes a metal layer ([0036], metal feature #124).
Regarding Claim 5 (currently amended), Chen in view of Son teaches the semiconductor chip as described in claim 1, wherein Chen further teaches the conductive layer (#124, Figure 6 of Chen annotated) includes a conductive pattern overlapping the signal pad (#506), the at least one heat dissipation pad (#506) and the through via (#115) on a plane.
Regarding Claim 6, Chen in view of Son teaches the semiconductor chip as described in claim 1, wherein Chen further teaches the heat dissipation structure (Figure 6 of Chen annotated) further includes an insulating layer (#122/#502, dielectric layer) and vias (#504, conductive vias),
the insulating layer (#122/#502) covering the conductive layer (#124), the vias (#504) penetrating the insulating layer, and the vias (#504) connecting the conductive layer (#124) to the signal pad and the at least one heat dissipation pad (#506) respectively.
Regarding Claim 7, Chen in view of Son teaches the semiconductor chip as described in claim 6, wherein Chen further teaches the insulating layer includes at least one of silicon oxide and silicon nitride ([0034-0035], dielectric #122/#502 comprises silicon oxide).
Regarding Claim 8, Chen in view of Son teaches the semiconductor chip as described in claim 6, wherein Chen further teaches a thickness of the insulating layer is 3.5 to 6 μm ([0022] & [0051], although not explicitly expressed, it is reasonable to apply an insulating layer such as #122/#502 similar to silicon oxide protective layer #108 with a thickness between 0.5 to 5μm).
Regarding Claim 10, Chen in view of Son teaches the semiconductor chip as described in claim 1, wherein Chen further teaches an insulating layer (#122, Figure 6) between the body (#102) and the conductive layer (#124).
Regarding Claim 11, Chen in view of Son teaches the semiconductor chip as described in claim 10, wherein Chen further teaches the insulating layer (#122, Figure 6) is on the body (#102).
Chen does not explicitly teach the insulating layer including a first insulating layer and a second insulating layer, the first insulating layer including silicon oxide, and the second insulating layer including silicon nitride, and
the second insulating layer is between the first insulating layer and the heat dissipation structure.
However, Son teaches the insulating layer (#580A, Figure 5, insulating layer) including a first insulating layer (#582A) and a second insulating layer (#584A), the first insulating layer including silicon oxide, and the second insulating layer including silicon nitride ([0082]), and
the second insulating layer (#584A) is between the first insulating layer (#582A) and the heat dissipation structure (#550P)
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Chen with the teaching of Son in order to protect the semiconductor chip and prevent current leakage due to metal diffusion according to [0047] of Son.
Regarding Claim 12, Chen in view of Son teaches the semiconductor chip as described in claim 1, wherein Chen further teaches the semiconductor chip includes a memory chip ([0025], the package structure includes device layer #203 with memory function).
Regarding Claim 13, Chen in view of Son teaches the semiconductor chip as described in claim 1, wherein Chen further teaches the at least one heat dissipation pad (Figure 6 of Chen annotated) includes a plurality of heat dissipation pads (#506) spaced apart from each other.
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Son, and further in view of US20210225708A1; Lee et al.; (hereinafter “Lee”).
Regarding Claim 4, Chen in view of Son teaches the semiconductor chip as described in claim 1.
Chen in view of Son does not explicitly teach a thickness of the conductive layer is 3 to 5 μm.
However, Lee teaches chip-on-chip package ([0023]), wherein a thickness of a conductive layer is 3 to 5 μm (Figures 11A-C, [242], metal layer #27 of backside interconnection structure #79 for heat dissipation function can have a thickness of such as 5 μm).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have selected the overlapping portion of the ranges disclosed by Lee in order to provide power/ground planes for power supply or heat dissipater for the device according to Lee, [0242]. See also MPEP 2144.04.
Regarding Claim 9, Chen in view of Son teaches the semiconductor chip as described in claim 6.
Chen in view of Son does not explicitly teach a diameter of the vias is 3 to 10 μm.
However, Lee teaches a diameter of the vias is 3 to 10 μm (Figures 1E or 11A-C, [0116], diameter of via openings #14a is between 0.5-20 μm).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have selected the overlapping portion of the ranges disclosed by Lee in order to provide a through via structure connecting metal pads to underlaying metal layers according to Lee, [0116]. See also MPEP 2144.04.
Claims 14-15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of US20230402340A1; Lin et al.; (hereinafter “Lin”).
Regarding Claim 14 (currently amended), Jin teaches a semiconductor package (#2390a-e, Figures 19A-E) comprising:
a first semiconductor chip (#2300a); and
a plurality of second semiconductor chips (#2300b-d) stacked on the first semiconductor chip,
wherein each second semiconductor chip of the plurality of second semiconductor chips (#2300b-d) includes
a body (#150, Figure 11B, [0231]) having a front surface (#150fs) and a rear surface (#150bs);
a wiring structure (wiring line #118a/b and insulating layer #121) above the front surface of the body (#150fs);
a through via (#115) penetrating the body (#150), and the through via being connected to the wiring structure (#118a),
a heat dissipation structure ([0171-0173]) above the rear surface of the body (#150bs), and the heat dissipation structure including a conductive layer (#164/#166g) connected to the through via (#115), and
a signal pad (#164io) and at least one heat dissipation pad (#166g_g) on the heat dissipation structure, and the signal pad and the heat dissipation pad being connected to the conductive layer ([0172], support portions #166g_1/#166g_2 can continuously connect conductive patterns #164/#166g),
the first semiconductor chip includes a memory chip, and each second semiconductor chip of the plurality of second semiconductor chips includes a memory chip (Figure 20, [0298], memory device 2420 can comprise semiconductor devices/package as described in Figures 19A-E).
the signal pad and the heat dissipation pad of each second semiconductor chip of the plurality of second semiconductor chips face another second semiconductor chip of the plurality of second semiconductor chips thereabove (Figures 19A-E, [0178], backside conductive pads connect the chips in the stack).
Jin does not explicitly teach the first semiconductor chip includes a memory controller chip.
However, Lin teaches a semiconductor die comprising stacked memory dies ([0023-0024]), wherein a first semiconductor chip includes a memory controller chip ([0023], die #120 comprises stacked High-Bandwidth-Memory dies and controller die).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Jin with the teaching of Lin in order to provide a controller die in stacked memory dies for controlling the dies’ operation according to Lin, [0023].
Regarding Claim 15, Jin in view of Lin teaches the package as described in claim 14, Jin further teaches the signal pad (#164io, Figure 11B) includes at least one of a power pad and a ground pad ([0169] or [0146]).
Regarding Claim 18, Jin in view of Lin teaches the package as described in claim 14, wherein Jin further teaches conductive bumps (#2381a-c, Figures 19A-E) on the signal pad and the heat dissipation pad (#2364-2366) of each of the plurality of second semiconductor chips (#2300a-d), the conductive bumps (#2381a-c) connecting the plurality of second semiconductor chips (#2300a-d) to each other.
Regarding Claim 19, Jin in view of Lin teaches the package as described in claim 14, wherein Jin further teaches an encapsulant (#2385, Figure 19A-E, [0231]) encapsulating the plurality of second semiconductor chips (#2300a-d).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Lin, and further in view of Chen.
Regarding Claim 16, Jin in view of Lin teaches the package as described in claim 14, wherein Jin further teaches the conductive layer includes a conductive pattern (#164/#166g, Figures 11B) overlapping the signal pad (#164io), the heat dissipation pad (#166g_g) OR the through via (#115) on a plane (horizontal/vertical plane).
Jin in view of Lin does not explicitly teach the conductive layer includes a conductive pattern overlapping the signal pad, the heat dissipation pad AND the through via on a plane.
However, Chen teaches a conductive layer includes a conductive pattern (#124, Figure 6 of Chen annotated) overlapping the signal pad, the heat dissipation pad (#506, conductive pads connecting to electrical devices through via #115, although not explicitly disclosed, it is well known in electrical structure to use metal conductive element for signal/power routing and thermal management) and the through via (#504, conductive vias) on a plane (#124, #506 and 504 are vertically overlapped).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Jin with the teaching of Lin by known methods to yield predictable results (implementation an interconnect structure between device and conductive pads/bumps). See MPEP 2143(I)(A).
Regarding Claim 17, Jin in view of Lin teaches the package as described in claim 14.
Jin in view of Lin does not teach the heat dissipation structure further includes an insulating layer and vias, the insulating layer covering the conductive layer, the vias penetrating the insulating layer, and the vias connecting the conductive layer to the signal pad and the at least one heat dissipation pad respectively.
However, Chen teaches the heat dissipation structure (Figure 6 of Chen annotated, a conductive structure comprises conductive pads #506 and metal features #124 connecting to electrical devices through via #115, although not explicitly disclosed, it is well known in electrical structure to use metal conductive element for signal/power routing and thermal management) further includes an insulating layer (#122/#502, dielectric layer) and vias (#504, conductive vias),
the insulating layer (#122/#502) covering the conductive layer (#124), the vias (#504) penetrating the insulating layer (#502), and the vias (#504) connecting the conductive layer (#124) to the signal pad and the at least one heat dissipation pad (#506, conductive pads) respectively.
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Jin with the teaching of Lin by known methods to yield predictable results (implementation an interconnect structure between device and conductive pads/bumps). See MPEP 2143(I)(A).
Response to Arguments/Amendments
Applicant's amendment to claims 1 and corresponding arguments, pages 8-10 of the remarks, filed 06/30/2026, with respect to 35 U.S.C. 102(a)(1) rejection of claim 1 as unpatentable over Chen have been fully considered and are persuasive. Hence, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 as being unpatentable over Chen in view of Son. Son has been introduced in view of the amendment to claim 1 (see 35 U.S.C. 103 rejection of amended claim 1 above).
Applicant argues on page 9 of the remarks that Chen teaches conductive pads (#506) connecting to a single TSV (#115) which both primarily function as signal transferring elements in a package, and accordingly, pads (#506) of Chen only correspond to signal rear connection electrodes (#140S) and not power rear connection electrodes (#140P) disclosed by Son. However, examiner respectfully disagrees. Chen discloses conductive pads (#506) comprising metal material and electrically connecting to the dies, interconnect structure and TSV of the package according to [0036-0039], and does not limit the function of pads (#506) and TSVs (#115) to only signal transfer. It is well known in a package structure to use metal conductive element for signal/power routing and thermal management. Additionally, according to [0024-0025], device layer (#203) comprises various devices that function as memory, processor and power distribution, wherein (#203) connect to pads (#506) through multiple TSV (#115) and interconnect structure (#116), see Figure 6 of Chen annotated. Accordingly, conductive pads (#506) of Chen may correspond to rear connection electrodes (#140) including electrodes (#140D/140P/140S) disclosed by Son.
Applicant's amendment to claim 14 and corresponding arguments, pages 10-12 of the remarks, with respect to 35 U.S.C. 103 rejection of claim 14 as unpatentable over Chen in view of Son, evidenced by US20230402340A1; Lin et al.; (hereinafter “Lin”) have been fully considered and are persuasive. Hence, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 102(a)(1) as being unpatentable over Jin as evidenced by Lin. Jin has been introduced in view of the amendment to claim 14 (see 35 U.S.C. 102(a)(1) rejection of amended claim 14 above).
Applicant's amendment to claim 20 and corresponding arguments, pages 8-10 of the remarks, with respect to 35 U.S.C. 102(a)(1) rejection of claim 20 as unpatentable over Chen have been fully considered and are persuasive. Hence, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 102(a)(1) as being unpatentable over Jin. Jin has been introduced in view of the amendment to claim 20 (see 35 U.S.C. 102(a)(1) rejection of amended claim 20 above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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