DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-4 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specification
Amendment of Specification of 07/13/2026 is accepted. Specification objections made in the Non-Final Office Action mailed on 04/15/2026 are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuki et al. (US 2016/0133741 A1, hereinafter Matsuki ‘741) in view of Onozawa (US 2017/0018434 A1, hereinafter Onozawa ‘434), in view of the following arguments.
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With respect to Claim 1 Matsuki ‘741 discloses a silicon carbide semiconductor device (Fig 2A-3D and 5-6D (second embodiment)) comprising:
a semiconductor substrate (1/2/10/3/4/5, Fig 5, Para [0043-0045], hereinafter SS) that includes a substrate (1, Fig 5, Para [0043]) made of silicon carbide (1 made of SiC disclosed in Para [0043]) of a first or second conductivity type (Para [0043] discloses 1 as n type (first type)), a drift layer (2, Fig 5, Para [0043]) of the first conductivity type (Para [0043] discloses 2 as n type) disposed on the substrate (1) and having an impurity concentration lower than that of the substrate (1)(Para [0043] discloses drift layer 2 has a lower impurity concentration (3.0×1015/cm3) than substrate 1 (1.0×1019/cm3)), a base layer (3/5, Fig 5, Para [0044], hereinafter BL) of the second conductivity type (Para [0044] discloses BL as p type) disposed on (BL disposed on 2 shown in Fig 5) the drift layer (2), and an impurity region (4, Fig 5, Para [0044]) of the first conductivity type (Para [0044] discloses 4 as n-type) disposed in a surface layer portion (Fig 5 discloses 4 disposed in a surface layer portion of BL) of the base layer (BL);
a trench gate structure (6/8/9, Fig 5, Para [0048]) that includes a gate insulating film (8, Fig 5, Para [0048]) disposed on a wall surface (sides of trench 6 as disclosed in Fig 5) of a trench (6, Fig 5, Para [0048]) penetrating (Fig 5 discloses gate insulating film 8 on wall surface of trench 6 penetrating impurity region 4 and base BL and reaching drift region 2)) the impurity region (4) and the base layer (BL) and reaching the drift layer (2), and a gate electrode (9, Fig 5, Para [0048]) disposed on (disclosed in Fig 5) the gate insulating film (8);
a first electrode (11, Fig 5, Para [0052] discloses source electrode on structures 4,5,9) that is electrically connected (Para [0053] discloses 11 is electrically connected to impurity region 4 and base layer (through region 5)) to the impurity region (4) and the base layer (BL);
a second electrode (13, Fig 5, Para [0055]) that is electrically connected (13 electrically connected to substrate 1 disclosed in Para [0055]) to the substrate (1); and
an interlayer insulating film (9a/12, Fig 5, Para [0054], hereinafter IIF) that is disposed between (Fig 5 discloses 9a between gate electrode 9 and first electrode 11) the gate electrode (9) and the first electrode (11) to insulate, the gate electrode (9) and the first electrode (11) from each other (Examiner interprets “to insulate…from each other” as functional language MPEP2173.05(g) and therefore does not have patentable weight. However, Para [0049] of Matsuki ‘741 discloses 9a as an oxide which Examiner notes is the same material as interlayer insulating film 21 of the instant application (Para [0026]), therefore oxide interlayer insulating film 9a must behave the same insulating behavior as the oxide interlayer insulating film of the instant application), wherein
the gate electrode (9) is accommodated within (Fig 5 discloses 9 within trench 6) the trench (6),
the gate insulating film (8) has an extension portion (8a, Fig 5, Para [0048]) extending on (Fig 5 and Para [0048] discloses extension portion 8a of gate insulating film 8 on top of impurity region at left and right sides of trench 6 and on upper surface of semiconductor substrate) an uppermost surface (top surface of 4) of the impurity region (4) at a periphery (left and right sides of opening as shown in Fig 5) of an opening (opening of trench 6 as shown in Fig 5) of the trench (6) at an upper surface (top of SS) of the semiconductor substrate (SS),
the interlayer insulating film (IIF) includes a contact insulating film (9a, Fig 5, Para [0049]) that is in contact with the gate electrode (9) and the extension portion (8a) of the gate insulating film (8) (Fig 5 and Para [0085] disclose 9a in contact with gate electrode 9 and insulating film 8), and
the contact insulating film (9a) is a deposition film (Examiner interprets “is a deposition film” as functional language MPEP2173.05(g). The contact insulating film (9a) meets the structural limitations of the claim; Para [0049] of Matsuki ‘741 discloses 9a as an oxide which Examiner notes is the same material as interlayer insulating film 21 of the instant application (Para [0026]).
But Matsuki ‘741 fails to explicitly disclose a portion of the semiconductor substrate adjoining the trench has a termination structure in which dangling bonds are terminated with at least one selected from a group consisting of nitrogen, hydrogen, and phosphorus.
Nevertheless, in a related endeavor (Fig 1-7 of Onozawa ‘434), Onozawa ‘434 teaches a portion (34, Fig 5D of Onozawa ‘434, Para [0064]) of the semiconductor substrate (90, Fig 5D of Onozawa ‘434, Para [0064]) adjoining the trench (trench of 36/38, Fig 5D of Onozawa ‘434, Para [0043]) has a termination structure (disclosed in Para [0064] of Onozawa ‘434) in which dangling bonds (disclosed in Para [0064] and Fig 5D of Onozawa ‘434) are terminated with at least one selected from a group consisting of nitrogen, hydrogen, and phosphorus (Para [0009] and Fig 5D of Onozawa ‘434 disclose dangling bonds of 34 are terminated with hydrogen).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Onozawa ‘434’s teaching of a portion of the semiconductor substrate adjoining the trench has a termination structure in which dangling bonds are terminated with at least one selected from a group consisting of nitrogen, hydrogen, and phosphorus into Matsuki ‘741’s device. Matsuki ‘741 discloses a silicon carbide semiconductor structure with an insulated gate structure. Onozawa ‘434 also teaches a silicon carbide semiconductor structure with an insulated gate structure and further teaches a channel forming region around the sidewalls of the insulated gate. The ordinary artisan would have been motivated to modify Matsuki ‘741, therefore, in the manner set forth above, at least, because as Onozawa ‘434 teaches in Para [0064] that by terminating the dangling bonds that result from defects with hydrogen, “it is possible to reduce the leak current when the reverse voltage is applied and to reduce the variation of the gate threshold voltage (Vth)”.
As incorporated, the teaching of Onozawa ‘434 using hydrogen to terminate the dangling bonds of the gate insulating structure would be used in the device of Matsuki ‘741 in the trench gate structure (6/8/9 of Matsuki ‘741).
With respect to Claim 2 Matsuki ‘741 as modified by Onozawa ‘434 discloses all limitations of the silicon carbide semiconductor device according to claim 1, and Matsuki ‘741 further discloses wherein
the interlayer insulating film (IIF) has a shape protruding outward from the opening (opening of 6 as shown in Fig 5) of the trench (6) in a planar direction of the semiconductor substrate (SS)(annotated Fig 5 of Matsuki ‘741 discloses IIF protrudes outward from trench opening in planar direction of semi substrate).
With respect to Claim 6 Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360 discloses all limitations of the silicon carbide semiconductor device according to claim 1, but Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360 fails to expressly disclose wherein
a portion of the gate insulating film including the extension portion and being in contact with the impurity region has a thickness of 1.3 times or less a thickness of a portion of the gate insulating film disposed on the wall surface of the trench and in contact with the base layer.
Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360 fails to expressly disclose a portion of the gate insulating film including the extension portion and being in contact with the impurity region has a thickness of 1.3 times or less a thickness of a portion of the gate insulating film disposed on the wall surface of the trench and in contact with the base layer. However, it would be well-known to one of ordinary skill in the art that that thicknesses affect device properties and would impact desired device characteristics. One of ordinary skill in the art would have been led to the recited thicknesses through routine experimentation to achieve desired characteristics of the formed device. One of ordinary skill in the art would have a high expectation of success in forming the cited thickness of the extension portion of the gate insulating film as deposition processes are well-known for creating various thicknesses and there is a finite number of thicknesses for the gate insulating film extension portion. See MPEP§2144.05 (II)(A),(B).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuki ‘741 in view of Onozawa ‘434 and in further view of Hiyoshi et al. (US 2019/0074360 A1, hereinafter Hiyoshi ‘360), in view of the following arguments.
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With respect to Claim 3 Matsuki ‘741 discloses a manufacturing method of a silicon carbide semiconductor device (Fig 2A-6D (second embodiment and embodiment of Para [0095])), the semiconductor device including:
a semiconductor substrate (1/2/10/3/4/5, Fig 5, Para [0043-0045], hereinafter SS) that includes a substrate (1, Fig 5, Para [0043]) made of silicon carbide (1 made of SiC disclosed in Para [0043]) of a first or second conductivity type (Para [0043] discloses 1 as n type (first type)), a drift layer (2, Fig 5, Para [0043]) of the first conductivity type (Para [0043] discloses 2 as n type) disposed on the substrate (1) and having an impurity concentration lower than that of the substrate (1)(Para [0043] discloses drift layer 2 has a lower impurity concentration (3.0×1015/cm3) than substrate 1 (1.0×1019/cm3)), a base layer (3/5, Fig 5, Para [0044], hereinafter BL) of the second conductivity type (Para [0044] discloses BL as p type) disposed on (BL disposed on 2 shown in Fig 5) the drift layer (2), and an impurity region (4, Fig 5, Para [0044]) of the first conductivity type (Para [0044] discloses 4 as n-type) disposed in a surface layer portion (Fig 5 discloses 4 disposed in a surface layer portion of BL) of the base layer (BL);
a trench gate structure (6/8/9, Fig 5, Para [0048]) that includes a gate insulating film (8, Fig 5, Para [0048]) disposed on a wall surface (sides of trench 6 as disclosed in Fig 5) of a trench (6, Fig 5, Para [0048]) penetrating (Fig 5 discloses gate insulating film 8 on wall surface of trench 6 penetrating impurity region 4 and base BL and reaching drift region 2)) the impurity region (4) and the base layer (BL) and reaching the drift layer (2), and a gate electrode (9, Fig 5, Para [0048]) disposed on (disclosed in Fig 5) the gate insulating film (8);
a first electrode (11, Fig 5, Para [0052] discloses source electrode on structures 4,5,9) that is electrically connected (Para [0053] discloses 11 is electrically connected to impurity region 4 and base layer (through region 5)) to the impurity region (4) and the base layer (BL);
a second electrode (13, Fig 5, Para [0055]) that is electrically connected (13 electrically connected to substrate 1 disclosed in Para [0055]) to the substrate (1); and
an interlayer insulating film (9a/12, Fig 5, Para [0054], hereinafter IIF) that is disposed between (Fig 5 discloses 9a between gate electrode 9 and first electrode 11) the gate electrode (9) and the first electrode (11) to insulate, the gate electrode (9) and the first electrode (11) from each other (Para [0049] of Matsuki ‘741 discloses 9a as an oxide which Examiner notes is the same material as interlayer insulating film 21 of the instant application (Para [0026]), therefore oxide interlayer insulating film 9a must behave the same insulating behavior as the oxide interlayer insulating film of the instant application), wherein
the gate electrode (9) is accommodated within (Fig 5 discloses 9 within trench 6) the trench (6),
the gate insulating film (8) has an extension portion (8a, Fig 5, Para [0048]) extending on (Fig 5 and Para [0048] discloses extension portion 8a of gate insulating film 8 on top of impurity region at left and right sides of trench 6 and on upper surface of semiconductor substrate) an uppermost surface (top surface of 4) of the impurity region (4) at a periphery (left and right sides of opening as shown in Fig 5) of an opening (opening of trench 6 as shown in Fig 5) of the trench (6) at an upper surface (top of SS) of the semiconductor substrate (SS),
the interlayer insulating film (IIF) includes a contact insulating film (9a, Fig 5, Para [0049]) that is in contact with the gate electrode (9) and the extension portion (8a) of the gate insulating film (8) (Fig 5 and Para [0085] disclose 9a in contact with gate electrode 9 and insulating film 8), and
the contact insulating film (9a) is a deposition film (Para [0077 and 0087] disclose gate electrode 9 is deposited. Contact insulating film 9a is therefore an oxidized deposition film).
the manufacturing method of the silicon carbide semiconductor device, comprising:
preparing (process disclosed in Fig 2B-2D and 3C-3D, Para [0068-0070 and 0073-0076]) the semiconductor substrate (SS) formed with the base layer (BL), the impurity region (4), and the trench (6);
arranging (process disclosed in Fig 6A-6B and Para [0087]) the gate insulating film (8) on the wall surface (sides of trench 6 as disclosed in Fig 6A) of the trench (6) and on the upper surface (top of SS as shown in annotated Fig 5 of Matsuki ‘741) of the semiconductor substrate (SS);
arranging (process disclosed in Fig 6A-6B and Para [0087]) the gate electrode (9) on the gate insulating film (8) and within the trench (6);
arranging (process disclosed in Fig 6B-6D and Para [0088]) the interlayer insulating film (IIF) in a region including a portion (Fig 6D discloses IIF formed in a region including a portion above gate electrode 9) above the gate electrode (9); and
patterning (process disclosed in Fig 6D and Para [0088-0089]) the interlayer insulating film (IIF) so as to expose the impurity region (4) and the base layer (BL), wherein
the arranging (process disclosed in Fig 6B-6D and Para [0088-0089]) of the interlayer insulating film (IIF) includes forming the contact insulating film (9a) so that the contact insulating film (9a) is in contact with an upper surface (top of gate electrode 9) of the gate electrode (9) within the trench (6) and the extension portion (8a) of the gate insulating film (8)(Fig 6D discloses 9a in contact with top of gate electrode 9 within trench 6 and in contact with gate insulating film extension 8a), and
the arranging (process disclosed in Fig 3D and Para [0095]) of the gate insulating film (8) includes forming the gate insulating film (8) by a deposition method (Para [0095] discloses gate insulating film deposited by CVD).
But Matsuki ‘741 fails to explicitly disclose the semiconductor device having a portion of the semiconductor substrate adjoining the trench has a termination structure in which dangling bonds are terminated with at least one selected from a group consisting of nitrogen, hydrogen, and phosphorus.
Nevertheless, in a related endeavor (Fig 1-7 of Onozawa ‘434), Onozawa ‘434 teaches a portion (34, Fig 5D of Onozawa ‘434, Para [0064]) of the semiconductor substrate (90, Fig 5D of Onozawa ‘434, Para [0064]) adjoining the trench (trench of 36/38, Fig 5D of Onozawa ‘434, Para [0043]) has a termination structure (disclosed in Para [0064] of Onozawa ‘434) in which dangling bonds (disclosed in Para [0064] and Fig 5D of Onozawa ‘434) are terminated with at least one selected from a group consisting of nitrogen, hydrogen, and phosphorus (Para [0009] and Fig 5D of Onozawa ‘434 disclose dangling bonds of 34 are terminated with hydrogen).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Onozawa ‘434’s teaching of a portion of the semiconductor substrate adjoining the trench has a termination structure in which dangling bonds are terminated with at least one selected from a group consisting of nitrogen, hydrogen, and phosphorus into Matsuki ‘741’s device. Matsuki ‘741 discloses a silicon carbide semiconductor structure with an insulated gate structure. Onozawa ‘434 also teaches a silicon carbide semiconductor structure with an insulated gate structure and further teaches a channel forming region around the sidewalls of the insulated gate. The ordinary artisan would have been motivated to modify Matsuki ‘741, therefore, in the manner set forth above, at least, because as Onozawa ‘434 teaches in Para [0064] that by terminating the dangling bonds that result from defects with hydrogen, “it is possible to reduce the leak current when the reverse voltage is applied and to reduce the variation of the gate threshold voltage (Vth)”.
As incorporated, the teaching of Onozawa ‘434 using hydrogen to terminate the dangling bonds of the gate insulating structure would be used in the device of Matsuki ‘741 in the trench gate structure (6/8/9 of Matsuki ‘741).
And Matsuki ‘741 as modified by Onozawa ‘434 discloses the method forming the termination structure by bonding the at least one selected from the group consisting of nitrogen, hydrogen, and phosphorus to the dangling bonds in the portion of the semiconductor substrate adjoining the trench (6 as modified above) (Para [0009 and 0064] disclose dangling bonds of 34 are terminated with hydrogen and Para [0064] and Fig 5D of Onozawa ‘434 discloses dangling bond termination process step of forming a hydrogen-silicon bond).
But Matsuki ‘741 as modified by Onozawa ‘434 discloses fails to expressly disclose forming the contact insulating film by a deposition method.
Nevertheless, in a related endeavor (Fig 1 and 13 of Hiyoshi ‘360), Hiyoshi ‘360 teaches forming the contact insulating film (22, Fig 1 and 13, Para [0127]) by a deposition method. (Para [0127] discloses forming insulating film using CVD).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Hiyoshi ‘360’s teaching of forming the contact insulating film by a deposition method into Matsuki ‘741 as modified by Onozawa ‘434’s method. Matsuki ‘741 disclose a process to deposit gate electrode in Para [0049] that then oxidizes a portion of that deposit to form an oxidized deposit film forming a contact insulating film. Hiyoshi ‘360 teaches that a contact insulating film can be a directly deposited dielectric material using a CVD process. The ordinary artisan would have been motivated to modify Matsuki ‘741 as modified by Onozawa ‘434 in the manner set forth above, at least, because using the teaching of Hiyoshi ‘360 of directly depositing the dielectric insulating film would be using a well-known process with a high expectation of success of depositing dielectric films and further it would simplify the steps of the Matsuki ‘741 as modified by Onozawa ‘434 process as it eliminates the oxidation steps used to form 9a of Matsuki ’741 and could continue to use the CVD chamber from the formation of the gate electrode 9 of Matsuki ‘741.
As incorporated, the CVD process for forming an insulating film of Hiyoshi ‘360 would be used to form the contact insulating film (9a) of Matsuki ‘741 as modified by Onozawa ‘434.
With respect to Claim 4 Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360 discloses all limitations of the manufacturing method according to claim 3, and Matsuki ‘741 further discloses wherein
in the patterning (process disclosed in Fig 6D and Para [0088-0089]) of the interlayer insulating film (IIF), the interlayer insulating film (IIF) is patterned so that the interlayer insulating film (IIF) has a shape protruding outward from the opening (opening of 6 as shown in Fig 5) of the trench (6) in a planar direction of the semiconductor substrate (SS)(annotated Fig 5 of Matsuki ‘741 discloses IIF protrudes outward from trench opening in planar direction of semi substrate).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuki ‘741 in view of Onozawa ‘434 in view of Hiyoshi ‘360 and in further view of Hiyoshi et al. (US 2014/0042453 A1, hereinafter Hiyoshi ‘453), in view of the following arguments.
With respect to Claim 7 Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360 discloses all limitations of the manufacturing method according to claim 3, but Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360 fails to expressly disclose wherein
the forming of the termination structure includes performing a heat treatment in an oxygen and nitrogen atmosphere.
Nevertheless, in a related endeavor (Fig 1-3 and 6 of Hiyoshi ‘453), Hiyoshi ‘453 teaches the forming of the termination structure includes performing a heat treatment in an oxygen and nitrogen atmosphere. (Fig 1-3 and 6 and Para [0011-0012 and 0070-0071] teaches a two-step process to terminate dangling bonds of a silicon carbide substrate using a heat treatment in an oxygen atmosphere in the first step and a heat treatment in a nitrogen atmosphere in the second step).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Hiyoshi ‘453’s teaching of the forming of the termination structure includes performing a heat treatment in an oxygen and nitrogen atmosphere into Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360’s method. Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360 discloses a heat treatment process for terminating the dangling bonds of a silicon carbide substrate and is open to the process steps as it provides few details of the process steps. Hiyoshi ‘453 teaches a detailed heat treatment process terminating the dangling bonds of a silicon carbide substrate. The ordinary artisan would have been motivated to modify Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360 in the manner set forth above, at least, because as Hiyoshi ‘453 teaches in Para [0011 and 0071] using the process steps taught by Hiyoshi ‘453, nitrogen and phosphorus atoms can be trapped which will lead to a reduction in threshold voltage variation.
As incorporated, the forming of the termination structure includes performing a heat treatment in an oxygen and nitrogen atmosphere taught by Hiyoshi ‘453
would be used as the termination structure process of Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuki ‘741 in view of Onozawa ‘434 in view of Hiyoshi ‘360 and in further view of Shimizu (US 2024/0087897 A1, hereinafter Shimizu ‘897), in view of the following arguments.
With respect to Claim 8 Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360 discloses all limitations of the manufacturing method according to claim 3, but Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360 fails to expressly disclose wherein
the forming of the contact insulating film by the deposition method is performed after the forming of the termination structure.
Nevertheless, in a related endeavor (Fig 1-5 of Shimizu ‘897), Shimizu ‘897 teaches the forming of the contact insulating film (forming of contact insulating film 32 disclosed in, Fig 1 of Shimizu ‘897, Para [0097] and in process step S108) is performed after the forming of the termination structure (forming of the termination process disclosed in Para [0054 and 0085-0090] and in process step S105)(therefore forming the contact insulating film (step S105 is before step S108).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Shimizu ‘897’s teaching of the forming of the contact insulating film by the deposition method is performed after the forming of the termination structure into Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360’s method. Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360 discloses a silicon carbide MOSFET with a heat treatment process for terminating the dangling bonds of a silicon carbide substrate and a process for forming a contact insulating film. Shimizu ‘897 also teaches silicon carbide MOSFET with a heat treatment for terminating dangling bonds and the formation of a contact insulating film. The ordinary artisan would have been motivated to modify Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360 in the manner set forth above, at least, because as Shimizu ‘897 teaches in Para [0112] using the process steps taught by Shimizu ‘897 helps to reduce thermal distortion of insulating films.
As incorporated, the forming of the contact insulating film by the deposition method is performed after the forming of the termination structure taught by Shimizu ‘897 would be used so the process order of the forming of the contact insulating film deposition (9a of Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360) would be after the process of forming the termination structure as disclosed above in the method of Matsuki ‘741 as modified by Onozawa ‘434 and further modified by Hiyoshi ‘360.
Allowable Subject Matter
Claim 5 is allowed.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 5: Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature: “after the arranging of the contact insulating film, arranging a non-doped polysilicon; performing an ion-implantation to the non-doped polysilicon arranged in the temperature sensing section so as to form a temperature sensing element having a first conductivity type region and a second conductivity type region connected to each other; and removing the non-doped polysilicon arranged in the element section by using the contact insulating film as an etching stopper” along with the rest of the limitations of said claims
Closest prior art of record Mitani et al. (US 2020/0203526 A1) teaches a SiC semiconductor element, forming a trench in the element section and arranging a contact insulating film. However Mitani ‘526. fails to disclose the semiconductor substrate including an element section and a temperature sensing section is prepared, arranging a non-doped polysilicon; performing an ion-implantation to the non-doped polysilicon arranged in the temperature sensing section so as to form a temperature sensing element having a first conductivity type region and a second conductivity type region connected to each other; and removing the non-doped polysilicon arranged in the element section by using the contact insulating film as an etching stopper.
Closest prior art of record Onozawa (US 2017/0018434 A1) teaches a SiC semiconductor element, forming a trench in the element section and arranging a contact insulating film. However Onozawa ‘434 fails to disclose the semiconductor substrate including an element section and a temperature sensing section is prepared, arranging a non-doped polysilicon; performing an ion-implantation to the non-doped polysilicon arranged in the temperature sensing section so as to form a temperature sensing element having a first conductivity type region and a second conductivity type region connected to each other; and removing the non-doped polysilicon arranged in the element section by using the contact insulating film as an etching stopper.
Closest prior art of record Harrison et al. (US 2019/0172770 A1, hereinafter Harrison ‘770) teaches a SiC semiconductor element, forming a trench in the element section and arranging a contact insulating film, wherein in the preparing of the semiconductor substrate, the semiconductor substrate including an element section and a temperature sensing section is prepared, and the forming of the trench includes forming a trench in the element section, the method further comprising, arranging a non-doped polysilicon. However Harrison ‘770 fails to disclose after the arranging of the contact insulating film, performing an ion-implantation to the non-doped polysilicon arranged in the temperature sensing section so as to form a temperature sensing element having a first conductivity type region and a second conductivity type region connected to each other; and removing the non-doped polysilicon arranged in the element section by using the contact insulating film as an etching stopper.
Closest prior art of record Tomatsu et al. (US 5,998,268, hereinafter Tomatsu ‘268) teaches a SiC semiconductor element, forming a trench in the element section and arranging a contact insulating film, wherein in the preparing of the semiconductor substrate, the semiconductor substrate including an element section and a temperature sensing section is prepared, and the forming of the trench includes forming a trench in the element section, the method further comprising, arranging a non-doped polysilicon. However Tomatsu ‘268 fails to disclose after the arranging of the contact insulating film, performing an ion-implantation to the non-doped polysilicon arranged in the temperature sensing section so as to form a temperature sensing element having a first conductivity type region and a second conductivity type region connected to each other; and removing the non-doped polysilicon arranged in the element section by using the contact insulating film as an etching stopper.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Harrison et al. (US 2019/0172770 A1) teaches a SiC semiconductor element, forming a trench in the element section and arranging a contact insulating film, wherein in the preparing of the semiconductor substrate, the semiconductor substrate including an element section and a temperature sensing section is prepared, and the forming of the trench includes forming a trench in the element section, the method further comprising, arranging a non-doped polysilicon. Tomatsu et al. (US 5,998,268) teaches a SiC semiconductor element, forming a trench in the element section and arranging a contact insulating film, wherein in the preparing of the semiconductor substrate, the semiconductor substrate including an element section and a temperature sensing section is prepared, and the forming of the trench includes forming a trench in the element section, the method further comprising, arranging a non-doped polysilicon.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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