Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US PGPub 2024/0074193, hereinafter referred to as “Kim).
Kim discloses the semiconductor method as claimed. See figures 1-43 and corresponding text, where Kim teaches, in claim 1, a semiconductor memory device comprising: (figure 36-37; [0178-183])
a plurality of transistors;
a lower insulating structure covering the plurality of transistors;
a global line disposed within the lower insulating structure;
a mold insulating structure disposed over the lower insulating structure and including a first area overlapping the global line and a second area extending laterally from the first area;
a pass gate disposed in the first area of the mold insulating structure;
an active pillar passing through the pass gate and contacting the global line;
a pass gate insulating layer located between the active pillar and the pass gate;
a first conductive connection structure disposed in the second area of the mold insulating structure; and
a cell array structure including a plurality of memory cells arranged over the mold insulating structure. (figure 36-37; [0178-183])
Kim teaches, in claim 2, wherein the mold insulating structure comprises: a first insulating layer disposed over the lower insulating structure and extending along a bottom surface of the pass gate; a second insulating layer disposed over the first insulating layer and facing a side surface of the pass gate; and a third insulating layer disposed over the second insulating layer and extending along an upper surface of the pass gate (figure 36-37; [0178-183]).
Kim teaches, in claim 3, wherein the second insulating layer includes a material having an etch selectivity with respect to the first insulating layer and the third insulating layer (figure 36-37; [0178-183]).
Kim teaches, in claim 4, wherein the plurality of transistors comprises:
a first transistor overlapping the first area of the mold insulating structure; and
a second transistor overlapping the second area of the mold insulating structure (figure 36-37; [0178-183]).
Kim teaches, in claim 5, wherein the first transistor is included in a block decoder configured to output a block select signal transmitted to the pass gate (figure 36-37; [0178-183]).
Kim teaches, in claim 6, further comprising: a conductive lower connection structure disposed inside the lower insulating structure and connected to the second transistor; and a first conductive connection structure contacting the conductive lower connection structure and extending into the second area of the mold insulating structure (figure 36-37; [0178-183]).
Kim teaches, in claim 7, wherein the active pillar comprises:
a channel layer including a horizontal portion contacting the global line and a vertical portion extending from the horizontal portion toward the cell array structure; and
a semiconductor capping pattern disposed in a central region of the vertical portion in the channel layer (figure 36-37; [0178-183]).
Kim teaches, in claim 8, wherein the horizontal portion of the channel layer and the semiconductor capping pattern include an impurity of the same conductivity type (figure 36-37; [0178-183]).
Kim teaches, in claim 9, further comprising: a plurality of slits disposed spaced apart from each other inside the pass gate (figure 36-37; [0178-183]).
Kim teaches, in claim 10, wherein the cell array structure comprises:
a gate stack including a plurality of conductive layers spaced apart from each other and stacked in a first direction opposite to a direction toward the mold insulating structure over the mold insulating structure;
a channel layer passing through the gate stack; and
a memory layer between the channel layer and the gate stack (figure 36-37; [0178-183]).
Kim teaches, in claim 11, further comprising: (figure 36-37; [0178-183])
a first intervening insulating structure disposed between the gate stack and the mold insulating structure;
a conductive connection structure disposed inside the first intervening insulating structure and connected to the active pillar;
a second intervening insulating structure disposed between the first intervening insulating structure and the gate stack;
a first conductive bonding structure disposed inside the second intervening insulating structure and connected to the conductive connection structure;
a third intervening insulating structure disposed between the second intervening insulating structure and the gate stack;
a second conductive bonding structure disposed inside the third intervening insulating structure and bonded to the first conductive bonding structure; and
a gate contact plug extending from a conductive layer corresponding to the second conductive bonding structure among the plurality of conductive layers toward the second conductive bonding structure.
Kim teaches, in claim 12, further comprising: (figure 36-37; [0178-183])
a first intervening insulating structure disposed between the gate stack and the mold insulating structure;
a conductive connection structure disposed inside the first intervening insulating structure and connected to the active pillar;
a second intervening insulating structure disposed between the first intervening insulating structure and the gate stack;
a doped semiconductor structure disposed between the second intervening insulating structure and the gate stack and connected to the channel layer; and
a plurality of gate contact plugs respectively connected to the plurality of conductive layers and extending in the first direction.
Kim teaches, in claim 13, a semiconductor memory device comprising: (figure 36-37; [0178-183])
a first peripheral circuit structure including a block decoder;
a gate stacked apart from the first peripheral circuit structure in a first direction and including a plurality of conductive layers spaced apart and stacked in the first direction;
a mold insulating structure disposed between the gate stack and the first peripheral circuit structure and including a first area overlapping the block decoder and a second area extending laterally from the first area; and
a second peripheral circuit structure disposed within the first area of the mold insulating structure and including a plurality of pass transistors configured to operate in response to a block select signal output from the block decoder.
Kim teaches, in claim 14, wherein each pass transistor of the plurality of pass transistors comprises: (figure 36-37; [0178-183])
a pass gate disposed in the first area of the mold insulating structure;
an active pillar passing through the pass gate; and
a pass gate insulating layer located between the active pillar and the pass gate.
Lee teaches, in claim 15, further comprising:
a lower insulating structure disposed between the first peripheral circuit structure and the mold insulating structure; and
a global line disposed within the lower insulating structure and contacting the active pillar. (figure 36-37; [0178-183])
Kim teaches, in claim 16, further comprising(figure 36-37; [0178-183])
a plurality of slits disposed spaced apart from each other inside the pass gate.
Lee teaches, in claim 17, wherein the mold insulating structure comprises:
a first insulating layer extending along a bottom surface of the pass gate and penetrated by the active pillar;
a second insulating layer disposed over the first insulating layer and facing a side surface of the pass gate ; and
a third insulating layer disposed over the second insulating layer and extending along an upper surface of the pass gate.
Kim teaches, in claim 18, wherein the second insulating layer includes a material having an etch selectivity with respect to the first insulating layer and the third insulating layer. (figure 36-37; [0178-183])
Kim teaches, in claim 19, further comprising(figure 36-37; [0178-183])
a plurality of first conductive bonding structures connected to the plurality of pass transistors; a channel layer passing through the gate stack;
a memory layer between the channel layer and the gate stack;
a plurality of gate contact plugs respectively contacting the plurality of conductive layers and extending toward the plurality of pass transistors; and
a plurality of second conductive bonding structures respectively connected to the plurality of gate contact plugs and respectively bonded to the plurality of first conductive bonding structures.
Kim teaches, in claim 20, further comprising:
a channel layer passing through the gate stack;
a memory layer (20) between the channel layer and the gate stack;
a doped semiconductor structure disposed between the gate stack and the mold insulating structure and connected to the channel layer; and
a plurality of gate contact plugs respectively contacting the plurality of conductive layers and extending in the first direction (figure 36-37; [0178-183]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STANETTA D ISAAC/Examiner, Art Unit 2898 September 19, 2026\
Prosecution Insights