Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10, 11, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20060267173 to Takiar et al. (Takiar) in view of U.S. Pat. Pub. No. 20190131203 to Kang et al. (Kang) and further in view of U.S. Pat. Pub. No. 20200135656 to Zhou et al. (Zhou) and further in view of TW I249232 to Huang et al. (Huang).
Regarding Claim 1, Takiar teaches in Fig. 7B at least, a semiconductor device comprising:
a substrate 702;
a controller 720 disposed on the substrate;
a nonvolatile memory 704-710 disposed on the substrate to be separated from the controller; and
a first resin [0069] sealing body sealing the controller, the nonvolatile memory.
Takiar does not explicitly teach a first heat sink disposed in contact with an upper surface of the controller, the resin sealing the first heat sink, wherein the first heat sink is exposed on at least one surface selected from the group consisting of an upper surface and a side surface of the first resin sealing body.
However, in analogous art, Kang teaches a first heat sink 805 disposed in contact with an upper surface of the controller, a resin encapsulating the first heat sink, wherein the first heat sink is exposed on at least one surface selected from the group consisting of an upper surface and a side surface of the first resin sealing body (see Fig. 3). It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Kang to extract waste heat from the controller to improve performance.
Takiar and Kang do not explicitly teach a second heat sink disposed in contact with an upper surface of the nonvolatile memory; and the resin seals the second heat sink, and the second heat sink is exposed at a surface of the resin.
However, in analogous art, Zhou teaches in Fig. 1 at least, a heat sink 150 on a stack of nonvolatile memory 120 that is exposed from a sealing resin 140. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Zhou to extract heat from the memory devices, thereby improving performance.
The person of ordinary skill having the benefit of Takiar, Kang and Zhou can readily move the memory stack and controller on a substrate to achieve the thermal benefits taught by Kang and Zhou.
Furthermore, Huang teaches in Fig. 12 at least that heat sinks 1230 may be configured to be exposed on a top and side surface of an encapsulant 127. It would have been obvious to the person of ordinary skill in the art before the time of filing to modify Takiar, Kang and Zhou with heat sinks being exposed on multiple surfaces to better dissipate heat.
Regarding Claim 2, Takiar, Kang, Zhou and Huang teach the semiconductor device according to claim 1, wherein a thickness of the first heat sink is thicker than a thickness of the second heat sink (in the combination of Kang and Zhou this would be the case by necessity).
Regarding Claim 3, Takiar, Kang, Zhou and Huang teach the semiconductor device according to claim 1, further comprising:
a wiring disposed in the substrate (PCB has wiring therein, [0030]);
a bonding wire electrically connecting the wiring to the controller and the nonvolatile memory, on the substrate; and
a solder ball electrically connected to the wiring (although not shown, it is well within the knowledge of the person of ordinary skill to add solder balls to the bottom of the substrate to integrate the device into application), wherein the controller includes a first one end, and a first other end opposite to the first one end, and the nonvolatile memory includes a second one end, and a second other end opposite to the second one end, wherein the bonding wire includes a first bonding wire electrically connected to the first one end and a second bonding wire electrically connected to the first other end, on the controller, and a third bonding wire electrically connected to the second one end and a fourth bonding wire electrically connected to the second other end, on the nonvolatile memory, wherein the first heat sink is disposed between the first bonding wire and the second bonding wire, on the controller, in planar view, and the second heat sink is disposed between the third bonding wire and the fourth bonding wire, on the nonvolatile memory, in planar view (see for example the embodiment of Fig. 3 of Takiar showing a stacked/ staggered arrangement, the heat sinks of Kang and Zhou would be mounted according to the claim).
Regarding Claims 10 and 11, Takiar, Kang, Zhou and Huang teach the semiconductor device according to claim 2, wherein an area of the second heat sink exposed on the upper surface of the first resin sealing body is larger than an area of the first heat sink exposed on the side surface of the first resin sealing body (all cited references show the memory ICs to be substantially greater in area than the control IC, and it would follow naturally for the person of ordinary skill to maximize the area of the heat sink on the memory and controller respectively to maximize thermal transfer, leading to the arrangement).
Claims 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Takiar, Kang and Zhou as applied to claim 10 above, and further in view of U.S. Pat. Pub. No. 20200091129 to Fujimaki.
Regarding Claims 12 and 18, Takiar, Kang, Zhou and Huang teach the semiconductor device according to claim 10, but do not explicitly teach a fourth external heat sink disposed to be in contact with the first heat sink and the second heat sink and to cover the first heat sink and the second heat sink, on the upper surface and the side surface on the first resin sealing body.
However, in analogous art, Fujimaki teaches an external heat sink 26 similarly positioned such that the first and second heat sinks of Kang and Zhou would be in contact. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Fujimaki for greater thermal dissipation, as taught by Fujimaki [0065].
Fujimaki is silent regarding the material of the external heat sink 26. However, aluminum and copper are the two most commonly used metals for heat dissipation in semiconductor packages, and given the lack of specifics by Fujimaki, the person of ordinary skill would be motivated to begin experimenting with the most well known and studied materials.
Regarding Claims 19 and 20, Takiar, Kang, Zhou and Huang teach an electronic device comprising: a circuit substrate; the semiconductor device according to claim 1 mounted on the circuit substrate; semiconductor device according to claim 10, but do not explicitly teach and a host controller mounted on the circuit substrate, the host controller configured to control the semiconductor device and further comprising: a volatile memory mounted on the circuit substrate, the volatile memory temporarily storing data for the host controller; a power supply circuit mounted on the circuit substrate, the power supply circuit configured to supply electric power to the host controller, the semiconductor device, and the volatile memory; and a housing for housing the circuit substrate. However, these are all common elements of commercially available DDR5 RAM sticks. See for example https://www.rambus.com/memory-interface-chips/ddr5-dimm-chipset/.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EVREN SEVEN/ Primary Examiner, Art Unit 2812
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